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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-07-22 22:59:22 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-07-22 23:02:58 +0300 |
| commit | af8fa36bf0cf6a09d6f4d9ad16eab30bc2ec8719 (patch) | |
| tree | a9397811949aefdb90f7791ce713455fa04985f1 /llvm/lib | |
| parent | a4e964a2821905728b866fb64784fbea1f67ccc1 (diff) | |
| download | llvm-af8fa36bf0cf6a09d6f4d9ad16eab30bc2ec8719.zip llvm-af8fa36bf0cf6a09d6f4d9ad16eab30bc2ec8719.tar.gz llvm-af8fa36bf0cf6a09d6f4d9ad16eab30bc2ec8719.tar.bz2 | |
[NFCI][TLI] prepare[US]REMEqFold(): don't add nonsensical 'exact' flag to rotates created
As pointed out by Craig Topper.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 71e90c3..79b347b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -5630,10 +5630,8 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode, // We need ROTR to do this. if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) return SDValue(); - SDNodeFlags Flags; - Flags.setExact(true); // UREM: (rotr (mul N, P), K) - Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); + Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); Created.push_back(Op0.getNode()); } @@ -5897,10 +5895,8 @@ TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode, // We need ROTR to do this. if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) return SDValue(); - SDNodeFlags Flags; - Flags.setExact(true); // SREM: (rotr (add (mul N, P), A), K) - Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags); + Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal); Created.push_back(Op0.getNode()); } |