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author | Thorsten Schütt <schuett@gmail.com> | 2024-11-11 10:45:02 +0100 |
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committer | GitHub <noreply@github.com> | 2024-11-11 10:45:02 +0100 |
commit | a5d09f4ad94fab718e787fb6dce7933e7742eb1b (patch) | |
tree | d3c9b42d7786c5a3b3c0353f41f30f27eafb4e59 /llvm/lib | |
parent | a4e507df7a07f234350669395d3521ed343a06ea (diff) | |
download | llvm-a5d09f4ad94fab718e787fb6dce7933e7742eb1b.zip llvm-a5d09f4ad94fab718e787fb6dce7933e7742eb1b.tar.gz llvm-a5d09f4ad94fab718e787fb6dce7933e7742eb1b.tar.bz2 |
[GlobalISel] Add G_STEP_VECTOR instruction (#115598)
aka llvm.stepvector Intrinsic
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 11 | ||||
-rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 30 |
2 files changed, 41 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 02dbe78..c5e5c92 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -809,6 +809,17 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res, return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)}); } +MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res, + unsigned Step) { + ConstantInt *CI = + ConstantInt::get(getMF().getFunction().getContext(), APInt(64, Step)); + auto StepVector = buildInstr(TargetOpcode::G_STEP_VECTOR); + StepVector->setDebugLoc(DebugLoc()); + Res.addDefToMIB(*getMRI(), StepVector); + StepVector.addCImm(CI); + return StepVector; +} + MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res, unsigned MinElts) { diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 10369928..3910046 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1731,6 +1731,36 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { } break; } + case TargetOpcode::G_STEP_VECTOR: { + if (!MI->getOperand(1).isCImm()) { + report("operand must be cimm", MI); + break; + } + + if (!MI->getOperand(1).getCImm()->getValue().isStrictlyPositive()) { + report("step must be > 0", MI); + break; + } + + LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); + if (!DstTy.isScalableVector()) { + report("Destination type must be a scalable vector", MI); + break; + } + + // <vscale x 2 x p0> + if (!DstTy.getElementType().isScalar()) { + report("Destination element type must be scalar", MI); + break; + } + + if (MI->getOperand(1).getCImm()->getBitWidth() != + DstTy.getElementType().getScalarSizeInBits()) { + report("step bitwidth differs from result type element bitwidth", MI); + break; + } + break; + } case TargetOpcode::G_INSERT_SUBVECTOR: { const MachineOperand &Src0Op = MI->getOperand(1); if (!Src0Op.isReg()) { |