[X86] movsd/movss/movd/movq - add support for constant comments (#78601)

If we're loading a constant value, print the constant (and the zero upper elements) instead of just the shuffle mask.

This did require me to move the shuffle mask handling into addConstantComments as we can't handle this in the MC layer.

2 files changed, 92 insertions, 30 deletions

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index 20b37d5..619328a 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -1212,15 +1212,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
   case X86::VMOVSDZrr:
     Src2Name = getRegName(MI->getOperand(2).getReg());
     Src1Name = getRegName(MI->getOperand(1).getReg());
-    [[fallthrough]];
-
-  case X86::MOVSDrm_alt:
-  case X86::MOVSDrm:
-  case X86::VMOVSDrm_alt:
-  case X86::VMOVSDrm:
-  case X86::VMOVSDZrm:
-  case X86::VMOVSDZrm_alt:
-    DecodeScalarMoveMask(2, nullptr == Src2Name, ShuffleMask);
+    DecodeScalarMoveMask(2, false, ShuffleMask);
     DestName = getRegName(MI->getOperand(0).getReg());
     break;
 
@@ -1229,15 +1221,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
   case X86::VMOVSSZrr:
     Src2Name = getRegName(MI->getOperand(2).getReg());
     Src1Name = getRegName(MI->getOperand(1).getReg());
-    [[fallthrough]];
-
-  case X86::MOVSSrm:
-  case X86::MOVSSrm_alt:
-  case X86::VMOVSSrm:
-  case X86::VMOVSSrm_alt:
-  case X86::VMOVSSZrm:
-  case X86::VMOVSSZrm_alt:
-    DecodeScalarMoveMask(4, nullptr == Src2Name, ShuffleMask);
+    DecodeScalarMoveMask(4, false, ShuffleMask);
     DestName = getRegName(MI->getOperand(0).getReg());
     break;
 
@@ -1248,22 +1232,10 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
   case X86::VMOVZPQILo2PQIrr:
   case X86::VMOVZPQILo2PQIZrr:
     Src1Name = getRegName(MI->getOperand(1).getReg());
-    [[fallthrough]];
-
-  case X86::MOVQI2PQIrm:
-  case X86::VMOVQI2PQIrm:
-  case X86::VMOVQI2PQIZrm:
     DecodeZeroMoveLowMask(2, ShuffleMask);
     DestName = getRegName(MI->getOperand(0).getReg());
     break;
 
-  case X86::MOVDI2PDIrm:
-  case X86::VMOVDI2PDIrm:
-  case X86::VMOVDI2PDIZrm:
-    DecodeZeroMoveLowMask(4, ShuffleMask);
-    DestName = getRegName(MI->getOperand(0).getReg());
-    break;
-
   case X86::EXTRQI:
     if (MI->getOperand(2).isImm() &&
         MI->getOperand(3).isImm())
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 0489026..fe3d16a 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1806,6 +1806,96 @@ static void addConstantComments(const MachineInstr *MI,
     break;
   }
 
+  case X86::MOVSDrm:
+  case X86::MOVSSrm:
+  case X86::VMOVSDrm:
+  case X86::VMOVSSrm:
+  case X86::VMOVSDZrm:
+  case X86::VMOVSSZrm:
+  case X86::MOVSDrm_alt:
+  case X86::MOVSSrm_alt:
+  case X86::VMOVSDrm_alt:
+  case X86::VMOVSSrm_alt:
+  case X86::VMOVSDZrm_alt:
+  case X86::VMOVSSZrm_alt:
+  case X86::MOVDI2PDIrm:
+  case X86::MOVQI2PQIrm:
+  case X86::VMOVDI2PDIrm:
+  case X86::VMOVQI2PQIrm:
+  case X86::VMOVDI2PDIZrm:
+  case X86::VMOVQI2PQIZrm: {
+    assert(MI->getNumOperands() >= (1 + X86::AddrNumOperands) &&
+           "Unexpected number of operands!");
+    int SclWidth = 32;
+    int VecWidth = 128;
+
+    switch (MI->getOpcode()) {
+    default:
+      llvm_unreachable("Invalid opcode");
+    case X86::MOVSDrm:
+    case X86::VMOVSDrm:
+    case X86::VMOVSDZrm:
+    case X86::MOVSDrm_alt:
+    case X86::VMOVSDrm_alt:
+    case X86::VMOVSDZrm_alt:
+    case X86::MOVQI2PQIrm:
+    case X86::VMOVQI2PQIrm:
+    case X86::VMOVQI2PQIZrm:
+      SclWidth = 64;
+      VecWidth = 128;
+      break;
+    case X86::MOVSSrm:
+    case X86::VMOVSSrm:
+    case X86::VMOVSSZrm:
+    case X86::MOVSSrm_alt:
+    case X86::VMOVSSrm_alt:
+    case X86::VMOVSSZrm_alt:
+    case X86::MOVDI2PDIrm:
+    case X86::VMOVDI2PDIrm:
+    case X86::VMOVDI2PDIZrm:
+      SclWidth = 32;
+      VecWidth = 128;
+      break;
+    }
+    std::string Comment;
+    raw_string_ostream CS(Comment);
+    const MachineOperand &DstOp = MI->getOperand(0);
+    CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
+
+    if (auto *C =
+            X86::getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
+      if (SclWidth == C->getType()->getScalarSizeInBits()) {
+        if (auto *CI = dyn_cast<ConstantInt>(C)) {
+          CS << "[";
+          printConstant(CI->getValue(), CS);
+          for (int I = 1, E = VecWidth / SclWidth; I < E; ++I) {
+            CS << ",0";
+          }
+          CS << "]";
+          OutStreamer.AddComment(CS.str());
+          break; // early-out
+        }
+        if (auto *CF = dyn_cast<ConstantFP>(C)) {
+          CS << "[";
+          printConstant(CF->getValue(), CS);
+          APFloat ZeroFP = APFloat::getZero(CF->getValue().getSemantics());
+          for (int I = 1, E = VecWidth / SclWidth; I < E; ++I) {
+            CS << ",";
+            printConstant(ZeroFP, CS);
+          }
+          CS << "]";
+          OutStreamer.AddComment(CS.str());
+          break; // early-out
+        }
+      }
+    }
+
+    // We didn't find a constant load, fallback to a shuffle mask decode.
+    CS << (SclWidth == 32 ? "mem[0],zero,zero,zero" : "mem[0],zero");
+    OutStreamer.AddComment(CS.str());
+    break;
+  }
+
 #define MOV_CASE(Prefix, Suffix)                                               \
   case X86::Prefix##MOVAPD##Suffix##rm:                                        \
   case X86::Prefix##MOVAPS##Suffix##rm:                                        \