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author | paperchalice <liujunchang97@outlook.com> | 2024-06-02 14:31:52 +0800 |
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committer | GitHub <noreply@github.com> | 2024-06-02 14:31:52 +0800 |
commit | 8917afaf0ec2ebe390284e3727e720eaf97967eb (patch) | |
tree | a27b331fbd47fb4e7623442371912eda70991487 /llvm/lib | |
parent | de37c06f01772e02465ccc9f538894c76d89a7a1 (diff) | |
download | llvm-8917afaf0ec2ebe390284e3727e720eaf97967eb.zip llvm-8917afaf0ec2ebe390284e3727e720eaf97967eb.tar.gz llvm-8917afaf0ec2ebe390284e3727e720eaf97967eb.tar.bz2 |
Revert "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94146)
This reverts commit de37c06f01772e02465ccc9f538894c76d89a7a1 to
de37c06f01772e02465ccc9f538894c76d89a7a1
It still breaks EXPENSIVE_CHECKS build. Sorry.
Diffstat (limited to 'llvm/lib')
86 files changed, 278 insertions, 671 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 2c1e557..8addaf1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -341,49 +341,9 @@ void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, // SelectionDAGISel code //===----------------------------------------------------------------------===// -SelectionDAGISelLegacy::SelectionDAGISelLegacy( - char &ID, std::unique_ptr<SelectionDAGISel> S) - : MachineFunctionPass(ID), Selector(std::move(S)) { - initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); - initializeBranchProbabilityInfoWrapperPassPass( - *PassRegistry::getPassRegistry()); - initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry()); - initializeTargetLibraryInfoWrapperPassPass(*PassRegistry::getPassRegistry()); -} - -bool SelectionDAGISelLegacy::runOnMachineFunction(MachineFunction &MF) { - // If we already selected that function, we do not need to run SDISel. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected)) - return false; - - // Do some sanity-checking on the command-line options. - if (EnableFastISelAbort && !Selector->TM.Options.EnableFastISel) - report_fatal_error("-fast-isel-abort > 0 requires -fast-isel"); - - // Decide what flavour of variable location debug-info will be used, before - // we change the optimisation level. - MF.setUseDebugInstrRef(MF.shouldUseDebugInstrRef()); - - // Reset the target options before resetting the optimization - // level below. - // FIXME: This is a horrible hack and should be processed via - // codegen looking at the optimization level explicitly when - // it wants to look at it. - Selector->TM.resetTargetOptions(MF.getFunction()); - // Reset OptLevel to None for optnone functions. - CodeGenOptLevel NewOptLevel = skipFunction(MF.getFunction()) - ? CodeGenOptLevel::None - : Selector->OptLevel; - - Selector->MF = &MF; - OptLevelChanger OLC(*Selector, NewOptLevel); - Selector->initializeAnalysisResults(*this); - return Selector->runOnMachineFunction(MF); -} - -SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOptLevel OL) - : TM(tm), FuncInfo(new FunctionLoweringInfo()), +SelectionDAGISel::SelectionDAGISel(char &ID, TargetMachine &tm, + CodeGenOptLevel OL) + : MachineFunctionPass(ID), TM(tm), FuncInfo(new FunctionLoweringInfo()), SwiftError(new SwiftErrorValueTracking()), CurDAG(new SelectionDAG(tm, OL)), SDB(std::make_unique<SelectionDAGBuilder>(*CurDAG, *FuncInfo, *SwiftError, @@ -401,17 +361,14 @@ SelectionDAGISel::~SelectionDAGISel() { delete SwiftError; } -void SelectionDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const { - CodeGenOptLevel OptLevel = Selector->OptLevel; +void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { if (OptLevel != CodeGenOptLevel::None) AU.addRequired<AAResultsWrapperPass>(); AU.addRequired<GCModuleInfo>(); AU.addRequired<StackProtector>(); AU.addPreserved<GCModuleInfo>(); AU.addRequired<TargetLibraryInfoWrapperPass>(); -#ifndef NDEBUG AU.addRequired<TargetTransformInfoWrapperPass>(); -#endif AU.addRequired<AssumptionCacheTracker>(); if (UseMBPI && OptLevel != CodeGenOptLevel::None) AU.addRequired<BranchProbabilityInfoWrapperPass>(); @@ -449,129 +406,65 @@ static void computeUsesMSVCFloatingPoint(const Triple &TT, const Function &F, } } -PreservedAnalyses -SelectionDAGISelPass::run(MachineFunction &MF, - MachineFunctionAnalysisManager &MFAM) { +bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { // If we already selected that function, we do not need to run SDISel. - if (MF.getProperties().hasProperty( + if (mf.getProperties().hasProperty( MachineFunctionProperties::Property::Selected)) - return PreservedAnalyses::all(); - + return false; // Do some sanity-checking on the command-line options. - if (EnableFastISelAbort && !Selector->TM.Options.EnableFastISel) - report_fatal_error("-fast-isel-abort > 0 requires -fast-isel"); + assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && + "-fast-isel-abort > 0 requires -fast-isel"); + + const Function &Fn = mf.getFunction(); + MF = &mf; + +#ifndef NDEBUG + StringRef FuncName = Fn.getName(); + MatchFilterFuncName = isFunctionInPrintList(FuncName); +#else + (void)MatchFilterFuncName; +#endif // Decide what flavour of variable location debug-info will be used, before // we change the optimisation level. - MF.setUseDebugInstrRef(MF.shouldUseDebugInstrRef()); + bool InstrRef = mf.shouldUseDebugInstrRef(); + mf.setUseDebugInstrRef(InstrRef); // Reset the target options before resetting the optimization // level below. // FIXME: This is a horrible hack and should be processed via // codegen looking at the optimization level explicitly when // it wants to look at it. - Selector->TM.resetTargetOptions(MF.getFunction()); - // Reset OptLevel to None for optnone functions. - // TODO: Add a function analysis to handle this. - Selector->MF = &MF; + TM.resetTargetOptions(Fn); // Reset OptLevel to None for optnone functions. - CodeGenOptLevel NewOptLevel = MF.getFunction().hasOptNone() - ? CodeGenOptLevel::None - : Selector->OptLevel; - - OptLevelChanger OLC(*Selector, NewOptLevel); - Selector->initializeAnalysisResults(MFAM); - Selector->runOnMachineFunction(MF); - - return getMachineFunctionPassPreservedAnalyses(); -} - -void SelectionDAGISel::initializeAnalysisResults( - MachineFunctionAnalysisManager &MFAM) { - auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(*MF) - .getManager(); - auto &MAMP = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(*MF); - Function &Fn = MF->getFunction(); -#ifndef NDEBUG - FuncName = Fn.getName(); - MatchFilterFuncName = isFunctionInPrintList(FuncName); -#else - (void)MatchFilterFuncName; -#endif + CodeGenOptLevel NewOptLevel = OptLevel; + if (OptLevel != CodeGenOptLevel::None && skipFunction(Fn)) + NewOptLevel = CodeGenOptLevel::None; + OptLevelChanger OLC(*this, NewOptLevel); TII = MF->getSubtarget().getInstrInfo(); TLI = MF->getSubtarget().getTargetLowering(); RegInfo = &MF->getRegInfo(); - LibInfo = &FAM.getResult<TargetLibraryAnalysis>(Fn); - GFI = Fn.hasGC() ? &FAM.getResult<GCFunctionAnalysis>(Fn) : nullptr; + LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(Fn); + GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr; ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn); - AC = &FAM.getResult<AssumptionAnalysis>(Fn); - auto *PSI = MAMP.getCachedResult<ProfileSummaryAnalysis>(*Fn.getParent()); + AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(mf.getFunction()); + auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI(); BlockFrequencyInfo *BFI = nullptr; - FAM.getResult<BlockFrequencyAnalysis>(Fn); if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOptLevel::None) - BFI = &FAM.getResult<BlockFrequencyAnalysis>(Fn); + BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI(); FunctionVarLocs const *FnVarLocs = nullptr; if (isAssignmentTrackingEnabled(*Fn.getParent())) - FnVarLocs = &FAM.getResult<DebugAssignmentTrackingAnalysis>(Fn); + FnVarLocs = getAnalysis<AssignmentTrackingAnalysis>().getResults(); - auto *UA = FAM.getCachedResult<UniformityInfoAnalysis>(Fn); - CurDAG->init(*MF, *ORE, MFAM, LibInfo, UA, PSI, BFI, FnVarLocs); - SwiftError->setFunction(*MF); - - // Now get the optional analyzes if we want to. - // This is based on the possibly changed OptLevel (after optnone is taken - // into account). That's unfortunate but OK because it just means we won't - // ask for passes that have been required anyway. - - if (UseMBPI && OptLevel != CodeGenOptLevel::None) - FuncInfo->BPI = &FAM.getResult<BranchProbabilityAnalysis>(Fn); - else - FuncInfo->BPI = nullptr; - - if (OptLevel != CodeGenOptLevel::None) - AA = &FAM.getResult<AAManager>(Fn); - else - AA = nullptr; - - SP = &FAM.getResult<SSPLayoutAnalysis>(Fn); - -#ifndef NDEBUG - TTI = &FAM.getResult<TargetIRAnalysis>(Fn); -#endif -} - -void SelectionDAGISel::initializeAnalysisResults(MachineFunctionPass &MFP) { - Function &Fn = MF->getFunction(); -#ifndef NDEBUG - FuncName = Fn.getName(); - MatchFilterFuncName = isFunctionInPrintList(FuncName); -#else - (void)MatchFilterFuncName; -#endif - - TII = MF->getSubtarget().getInstrInfo(); - TLI = MF->getSubtarget().getTargetLowering(); - RegInfo = &MF->getRegInfo(); - LibInfo = &MFP.getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(Fn); - GFI = Fn.hasGC() ? &MFP.getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) - : nullptr; - ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn); - AC = &MFP.getAnalysis<AssumptionCacheTracker>().getAssumptionCache(Fn); - auto *PSI = &MFP.getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI(); - BlockFrequencyInfo *BFI = nullptr; - if (PSI && PSI->hasProfileSummary() && OptLevel != CodeGenOptLevel::None) - BFI = &MFP.getAnalysis<LazyBlockFrequencyInfoPass>().getBFI(); - - FunctionVarLocs const *FnVarLocs = nullptr; - if (isAssignmentTrackingEnabled(*Fn.getParent())) - FnVarLocs = MFP.getAnalysis<AssignmentTrackingAnalysis>().getResults(); + ISEL_DUMP(dbgs() << "\n\n\n=== " << FuncName << "\n"); UniformityInfo *UA = nullptr; - if (auto *UAPass = MFP.getAnalysisIfAvailable<UniformityInfoWrapperPass>()) + if (auto *UAPass = getAnalysisIfAvailable<UniformityInfoWrapperPass>()) UA = &UAPass->getUniformityInfo(); - CurDAG->init(*MF, *ORE, &MFP, LibInfo, UA, PSI, BFI, FnVarLocs); + CurDAG->init(*MF, *ORE, this, LibInfo, UA, PSI, BFI, FnVarLocs); + FuncInfo->set(Fn, *MF, CurDAG); SwiftError->setFunction(*MF); // Now get the optional analyzes if we want to. @@ -580,32 +473,15 @@ void SelectionDAGISel::initializeAnalysisResults(MachineFunctionPass &MFP) { // ask for passes that have been required anyway. if (UseMBPI && OptLevel != CodeGenOptLevel::None) - FuncInfo->BPI = - &MFP.getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI(); + FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI(); else FuncInfo->BPI = nullptr; if (OptLevel != CodeGenOptLevel::None) - AA = &MFP.getAnalysis<AAResultsWrapperPass>().getAAResults(); + AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); else AA = nullptr; - SP = &MFP.getAnalysis<StackProtector>().getLayoutInfo(); - -#ifndef NDEBUG - TTI = &MFP.getAnalysis<TargetTransformInfoWrapperPass>().getTTI(Fn); -#endif -} - -bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { - const Function &Fn = mf.getFunction(); - - bool InstrRef = mf.shouldUseDebugInstrRef(); - - FuncInfo->set(MF->getFunction(), *MF, CurDAG); - - ISEL_DUMP(dbgs() << "\n\n\n=== " << FuncName << '\n'); - SDB->init(GFI, AA, AC, LibInfo); MF->setHasInlineAsm(false); @@ -900,8 +776,11 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { StringRef GroupName = "sdag"; StringRef GroupDescription = "Instruction Selection and Scheduling"; std::string BlockName; - bool MatchFilterBB = false; - (void)MatchFilterBB; + bool MatchFilterBB = false; (void)MatchFilterBB; +#ifndef NDEBUG + TargetTransformInfo &TTI = + getAnalysis<TargetTransformInfoWrapperPass>().getTTI(*FuncInfo->Fn); +#endif // Pre-type legalization allow creation of any node types. CurDAG->NewNodesMustHaveLegalTypes = false; @@ -926,7 +805,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif @@ -946,7 +825,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif @@ -968,7 +847,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif @@ -992,7 +871,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif } @@ -1010,7 +889,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif @@ -1026,7 +905,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif @@ -1046,7 +925,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif } @@ -1066,7 +945,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif @@ -1086,7 +965,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->dump()); #ifndef NDEBUG - if (TTI->hasBranchDivergence()) + if (TTI.hasBranchDivergence()) CurDAG->VerifyDAGDivergence(); #endif @@ -1674,6 +1553,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { } // Iterate over all basic blocks in the function. + StackProtector &SP = getAnalysis<StackProtector>(); for (const BasicBlock *LLVMBB : RPOT) { if (OptLevel != CodeGenOptLevel::None) { bool AllPredsVisited = true; @@ -1849,7 +1729,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { FastIS->recomputeInsertPt(); } - if (SP->shouldEmitSDCheck(*LLVMBB)) { + if (SP.shouldEmitSDCheck(*LLVMBB)) { bool FunctionBasedInstrumentation = TLI->getSSPStackGuardCheck(*Fn.getParent()); SDB->SPDescriptor.initialize(LLVMBB, FuncInfo->MBBMap[LLVMBB], @@ -1886,7 +1766,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { if (Fn.getParent()->getModuleFlag("eh-asynch")) reportIPToStateForBlocks(MF); - SP->copyToMachineFrameInfo(MF->getFrameInfo()); + SP.copyToMachineFrameInfo(MF->getFrameInfo()); SwiftError->propagateVRegs(); diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h index 0f0a22e..b70fbe4 100644 --- a/llvm/lib/Target/AArch64/AArch64.h +++ b/llvm/lib/Target/AArch64/AArch64.h @@ -85,7 +85,7 @@ void initializeAArch64CompressJumpTablesPass(PassRegistry&); void initializeAArch64CondBrTuningPass(PassRegistry &); void initializeAArch64ConditionOptimizerPass(PassRegistry&); void initializeAArch64ConditionalComparesPass(PassRegistry &); -void initializeAArch64DAGToDAGISelLegacyPass(PassRegistry &); +void initializeAArch64DAGToDAGISelPass(PassRegistry &); void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&); void initializeAArch64ExpandPseudoPass(PassRegistry &); void initializeAArch64GlobalsTaggingPass(PassRegistry &); diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 248778f..8fd58f4 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -44,11 +44,13 @@ class AArch64DAGToDAGISel : public SelectionDAGISel { const AArch64Subtarget *Subtarget; public: + static char ID; + AArch64DAGToDAGISel() = delete; explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<AArch64Subtarget>(); @@ -505,20 +507,11 @@ private: bool SelectAllActivePredicate(SDValue N); bool SelectAnyPredicate(SDValue N); }; - -class AArch64DAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit AArch64DAGToDAGISelLegacy(AArch64TargetMachine &tm, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<AArch64DAGToDAGISel>(tm, OptLevel)) {} -}; } // end anonymous namespace -char AArch64DAGToDAGISelLegacy::ID = 0; +char AArch64DAGToDAGISel::ID = 0; -INITIALIZE_PASS(AArch64DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(AArch64DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) /// isIntImmediate - This method tests to see if the node is a constant /// operand. If so Imm will receive the 32-bit value. @@ -6874,7 +6867,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { /// AArch64-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new AArch64DAGToDAGISelLegacy(TM, OptLevel); + return new AArch64DAGToDAGISel(TM, OptLevel); } /// When \p PredVT is a scalable vector predicate in the form diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 30f0ceaf..945ab5c 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -258,7 +258,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() { initializeAArch64StackTaggingPass(*PR); initializeAArch64StackTaggingPreRAPass(*PR); initializeAArch64LowerHomogeneousPrologEpilogPass(*PR); - initializeAArch64DAGToDAGISelLegacyPass(*PR); + initializeAArch64DAGToDAGISelPass(*PR); initializeAArch64GlobalsTaggingPass(*PR); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 46cc5f3..6016bd5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -81,7 +81,7 @@ struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> { PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); }; -void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); +void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); extern char &AMDGPUMachineCFGStructurizerID; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp index 7c353fd..01ab61a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp @@ -7,9 +7,7 @@ //===----------------------------------------------------------------------===// #include "AMDGPUCodeGenPassBuilder.h" -#include "AMDGPUISelDAGToDAG.h" #include "AMDGPUTargetMachine.h" -#include "llvm/Analysis/UniformityAnalysis.h" using namespace llvm; @@ -27,8 +25,6 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder( void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const { // TODO: Add passes pre instruction selection. - // Test only, convert to real IR passes in future. - addPass(RequireAnalysisPass<UniformityInfoAnalysis, Function>()); } void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass, @@ -36,7 +32,7 @@ void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass, // TODO: Add AsmPrinter. } -Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const { - addPass(AMDGPUISelDAGToDAGPass(TM)); +Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &) const { + // TODO: Add instruction selector. return Error::success(); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 3e2581d..e359573 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -98,9 +98,8 @@ static SDValue stripExtractLoElt(SDValue In) { } // end anonymous namespace -INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISelLegacy, "amdgpu-isel", - "AMDGPU DAG->DAG Pattern Instruction Selection", false, - false) +INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "amdgpu-isel", + "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo) INITIALIZE_PASS_DEPENDENCY(AMDGPUPerfHintAnalysis) INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass) @@ -108,20 +107,19 @@ INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) #endif -INITIALIZE_PASS_END(AMDGPUDAGToDAGISelLegacy, "amdgpu-isel", - "AMDGPU DAG->DAG Pattern Instruction Selection", false, - false) +INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "amdgpu-isel", + "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) /// This pass converts a legalized DAG into a AMDGPU-specific // DAG, ready for instruction scheduling. FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new AMDGPUDAGToDAGISelLegacy(TM, OptLevel); + return new AMDGPUDAGToDAGISel(TM, OptLevel); } AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel) { + : SelectionDAGISel(ID, TM, OptLevel) { EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG; } @@ -202,14 +200,14 @@ bool AMDGPUDAGToDAGISel::fp16SrcZerosHighBits(unsigned Opc) const { } } -void AMDGPUDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const { +void AMDGPUDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<AMDGPUArgumentUsageInfo>(); AU.addRequired<UniformityInfoWrapperPass>(); #ifdef EXPENSIVE_CHECKS AU.addRequired<DominatorTreeWrapperPass>(); AU.addRequired<LoopInfoWrapperPass>(); #endif - SelectionDAGISelLegacy::getAnalysisUsage(AU); + SelectionDAGISel::getAnalysisUsage(AU); } bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const { @@ -773,14 +771,10 @@ bool AMDGPUDAGToDAGISel::isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS, return false; } -StringRef AMDGPUDAGToDAGISelLegacy::getPassName() const { +StringRef AMDGPUDAGToDAGISel::getPassName() const { return "AMDGPU DAG->DAG Pattern Instruction Selection"; } -AMDGPUISelDAGToDAGPass::AMDGPUISelDAGToDAGPass(TargetMachine &TM) - : SelectionDAGISelPass( - std::make_unique<AMDGPUDAGToDAGISel>(TM, TM.getOptLevel())) {} - //===----------------------------------------------------------------------===// // Complex Patterns //===----------------------------------------------------------------------===// @@ -3613,9 +3607,4 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() { } while (IsModified); } -AMDGPUDAGToDAGISelLegacy::AMDGPUDAGToDAGISelLegacy(TargetMachine &TM, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<AMDGPUDAGToDAGISel>(TM, OptLevel)) {} - -char AMDGPUDAGToDAGISelLegacy::ID = 0; +char AMDGPUDAGToDAGISel::ID = 0; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index b5b374b..53d25b4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -83,14 +83,21 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel { bool fp16SrcZerosHighBits(unsigned Opc) const; public: + static char ID; + AMDGPUDAGToDAGISel() = delete; explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOptLevel OptLevel); + ~AMDGPUDAGToDAGISel() override = default; + + void getAnalysisUsage(AnalysisUsage &AU) const override; - bool runOnMachineFunction(MachineFunction &MF) override; bool matchLoadD16FromBuildVector(SDNode *N) const; + + bool runOnMachineFunction(MachineFunction &MF) override; void PreprocessISelDAG() override; void Select(SDNode *N) override; + StringRef getPassName() const override; void PostprocessISelDAG() override; protected: @@ -281,19 +288,4 @@ protected: #include "AMDGPUGenDAGISel.inc" }; -class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { -public: - AMDGPUISelDAGToDAGPass(TargetMachine &TM); -}; - -class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - - AMDGPUDAGToDAGISelLegacy(TargetMachine &TM, CodeGenOptLevel OptLevel); - - void getAnalysisUsage(AnalysisUsage &AU) const override; - StringRef getPassName() const override; -}; - #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index 57fc331..90f36fa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -71,9 +71,3 @@ FUNCTION_PASS_WITH_PARAMS( }, parseAMDGPUAtomicOptimizerStrategy, "strategy=dpp|iterative|none") #undef FUNCTION_PASS_WITH_PARAMS - -#ifndef MACHINE_FUNCTION_PASS -#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) -#endif -MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this)) -#undef MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 9c94ca1..dbbfe34 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -19,7 +19,6 @@ #include "AMDGPUCtorDtorLowering.h" #include "AMDGPUExportClustering.h" #include "AMDGPUIGroupLP.h" -#include "AMDGPUISelDAGToDAG.h" #include "AMDGPUMacroFusion.h" #include "AMDGPURegBankSelect.h" #include "AMDGPUSplitModule.h" @@ -388,7 +387,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeR600ExpandSpecialInstrsPassPass(*PR); initializeR600VectorRegMergerPass(*PR); initializeGlobalISel(*PR); - initializeAMDGPUDAGToDAGISelLegacyPass(*PR); + initializeAMDGPUDAGToDAGISelPass(*PR); initializeGCNDPPCombinePass(*PR); initializeSILowerI1CopiesPass(*PR); initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR); diff --git a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp index 28bcf72..293db13 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp @@ -48,17 +48,6 @@ protected: // Include the pieces autogenerated from the target description. #include "R600GenDAGISel.inc" }; - -class R600DAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit R600DAGToDAGISelLegacy(TargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<R600DAGToDAGISel>(TM, OptLevel)) {} -}; - -char R600DAGToDAGISelLegacy::ID = 0; - } // namespace bool R600DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { @@ -195,5 +184,5 @@ bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base, // DAG, ready for instruction scheduling. FunctionPass *llvm::createR600ISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new R600DAGToDAGISelLegacy(TM, OptLevel); + return new R600DAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 4d8667a..7cde09c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3087,12 +3087,9 @@ SDValue SITargetLowering::LowerFormalArguments( if (IsEntryFunc) allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics); - // DAG.getPass() returns nullptr when using new pass manager. - // TODO: Use DAG.getMFAM() to access analysis result. - if (DAG.getPass()) { - auto &ArgUsageInfo = DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); - ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo()); - } + auto &ArgUsageInfo = + DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); + ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo()); unsigned StackArgSize = CCInfo.getStackSize(); Info->setBytesInStackArgArea(StackArgSize); @@ -3304,13 +3301,9 @@ void SITargetLowering::passSpecialInputs( const AMDGPUFunctionArgInfo *CalleeArgInfo = &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo; if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) { - // DAG.getPass() returns nullptr when using new pass manager. - // TODO: Use DAG.getMFAM() to access analysis result. - if (DAG.getPass()) { - auto &ArgUsageInfo = - DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); - CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc); - } + auto &ArgUsageInfo = + DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); + CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc); } // TODO: Unify with private memory register handling. This is complicated by diff --git a/llvm/lib/Target/ARC/ARC.h b/llvm/lib/Target/ARC/ARC.h index 459f79c..b81016d 100644 --- a/llvm/lib/Target/ARC/ARC.h +++ b/llvm/lib/Target/ARC/ARC.h @@ -27,7 +27,7 @@ FunctionPass *createARCISelDag(ARCTargetMachine &TM, CodeGenOptLevel OptLevel); FunctionPass *createARCExpandPseudosPass(); FunctionPass *createARCOptAddrMode(); FunctionPass *createARCBranchFinalizePass(); -void initializeARCDAGToDAGISelLegacyPass(PassRegistry &); +void initializeARCDAGToDAGISelPass(PassRegistry &); } // end namespace llvm diff --git a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp index 5e6cfa5..17c2d7b 100644 --- a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp @@ -41,10 +41,12 @@ namespace { class ARCDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + ARCDAGToDAGISel() = delete; ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} void Select(SDNode *N) override; @@ -58,25 +60,17 @@ public: #include "ARCGenDAGISel.inc" }; -class ARCDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit ARCDAGToDAGISelLegacy(ARCTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<ARCDAGToDAGISel>(TM, OptLevel)) {} -}; - -char ARCDAGToDAGISelLegacy::ID; +char ARCDAGToDAGISel::ID; } // end anonymous namespace -INITIALIZE_PASS(ARCDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(ARCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) /// This pass converts a legalized DAG into a ARC-specific DAG, ready for /// instruction scheduling. FunctionPass *llvm::createARCISelDag(ARCTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new ARCDAGToDAGISelLegacy(TM, OptLevel); + return new ARCDAGToDAGISel(TM, OptLevel); } bool ARCDAGToDAGISel::SelectAddrModeImm(SDValue Addr, SDValue &Base, diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index 5f021cf..f50c3c0 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -97,7 +97,7 @@ MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo( extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() { RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeARCDAGToDAGISelLegacyPass(PR); + initializeARCDAGToDAGISelPass(PR); } TargetTransformInfo diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h index 0b7045e..b96e018 100644 --- a/llvm/lib/Target/ARM/ARM.h +++ b/llvm/lib/Target/ARM/ARM.h @@ -64,7 +64,7 @@ void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, void initializeARMBlockPlacementPass(PassRegistry &); void initializeARMBranchTargetsPass(PassRegistry &); void initializeARMConstantIslandsPass(PassRegistry &); -void initializeARMDAGToDAGISelLegacyPass(PassRegistry &); +void initializeARMDAGToDAGISelPass(PassRegistry &); void initializeARMExpandPseudoPass(PassRegistry &); void initializeARMFixCortexA57AES1742098Pass(PassRegistry &); void initializeARMLoadStoreOptPass(PassRegistry &); diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 7ffc643..20dd3e7 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -59,10 +59,12 @@ class ARMDAGToDAGISel : public SelectionDAGISel { const ARMSubtarget *Subtarget; public: + static char ID; + ARMDAGToDAGISel() = delete; explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(tm, OptLevel) {} + : SelectionDAGISel(ID, tm, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. @@ -360,19 +362,11 @@ private: /// selected when N would have been selected. void replaceDAGValue(const SDValue &N, SDValue M); }; - -class ARMDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - ARMDAGToDAGISelLegacy(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<ARMDAGToDAGISel>(tm, OptLevel)) {} -}; } -char ARMDAGToDAGISelLegacy::ID = 0; +char ARMDAGToDAGISel::ID = 0; -INITIALIZE_PASS(ARMDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) /// isInt32Immediate - This method tests to see if the node is a 32-bit constant /// operand. If so Imm will receive the 32-bit value. @@ -5892,5 +5886,5 @@ bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand( /// FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new ARMDAGToDAGISelLegacy(TM, OptLevel); + return new ARMDAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 7553778..4ef00df 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -110,7 +110,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() { initializeARMSLSHardeningPass(Registry); initializeMVELaneInterleavingPass(Registry); initializeARMFixCortexA57AES1742098Pass(Registry); - initializeARMDAGToDAGISelLegacyPass(Registry); + initializeARMDAGToDAGISelPass(Registry); } static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h index 0e67bb4..4b1336e 100644 --- a/llvm/lib/Target/AVR/AVR.h +++ b/llvm/lib/Target/AVR/AVR.h @@ -31,7 +31,7 @@ FunctionPass *createAVRExpandPseudoPass(); FunctionPass *createAVRFrameAnalyzerPass(); FunctionPass *createAVRBranchSelectionPass(); -void initializeAVRDAGToDAGISelLegacyPass(PassRegistry &); +void initializeAVRDAGToDAGISelPass(PassRegistry &); void initializeAVRExpandPseudoPass(PassRegistry &); void initializeAVRShiftExpandPass(PassRegistry &); diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp index 77db876..e67a1e2 100644 --- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp +++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp @@ -29,10 +29,12 @@ namespace { /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form). class AVRDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + AVRDAGToDAGISel() = delete; AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -58,19 +60,11 @@ private: const AVRSubtarget *Subtarget; }; -class AVRDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - AVRDAGToDAGISelLegacy(AVRTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<AVRDAGToDAGISel>(TM, OptLevel)) {} -}; - } // namespace -char AVRDAGToDAGISelLegacy::ID = 0; +char AVRDAGToDAGISel::ID = 0; -INITIALIZE_PASS(AVRDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(AVRDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { Subtarget = &MF.getSubtarget<AVRSubtarget>(); @@ -592,5 +586,5 @@ bool AVRDAGToDAGISel::trySelect(SDNode *N) { FunctionPass *llvm::createAVRISelDag(AVRTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new AVRDAGToDAGISelLegacy(TM, OptLevel); + return new AVRDAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp index a8c967f..e0776a6 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -95,7 +95,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() { auto &PR = *PassRegistry::getPassRegistry(); initializeAVRExpandPseudoPass(PR); initializeAVRShiftExpandPass(PR); - initializeAVRDAGToDAGISelLegacyPass(PR); + initializeAVRDAGToDAGISelPass(PR); } const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const { diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index 694d7ba..bbdbdbb 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -35,7 +35,7 @@ InstructionSelector *createBPFInstructionSelector(const BPFTargetMachine &, const BPFRegisterBankInfo &); void initializeBPFCheckAndAdjustIRPass(PassRegistry&); -void initializeBPFDAGToDAGISelLegacyPass(PassRegistry &); +void initializeBPFDAGToDAGISelPass(PassRegistry &); void initializeBPFMIPeepholePass(PassRegistry &); void initializeBPFMIPreEmitCheckingPass(PassRegistry&); void initializeBPFMIPreEmitPeepholePass(PassRegistry &); diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp index 67f98bd..7b8bcb2 100644 --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -46,10 +46,12 @@ class BPFDAGToDAGISel : public SelectionDAGISel { const BPFSubtarget *Subtarget; public: + static char ID; + BPFDAGToDAGISel() = delete; explicit BPFDAGToDAGISel(BPFTargetMachine &TM) - : SelectionDAGISel(TM), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. @@ -92,18 +94,11 @@ private: // Mapping from ConstantStruct global value to corresponding byte-list values std::map<const void *, val_vec_type> cs_vals_; }; - -class BPFDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - BPFDAGToDAGISelLegacy(BPFTargetMachine &TM) - : SelectionDAGISelLegacy(ID, std::make_unique<BPFDAGToDAGISel>(TM)) {} -}; } // namespace -char BPFDAGToDAGISelLegacy::ID = 0; +char BPFDAGToDAGISel::ID = 0; -INITIALIZE_PASS(BPFDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(BPFDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) // ComplexPattern used on BPF Load/Store instructions bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) { @@ -494,5 +489,5 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, } FunctionPass *llvm::createBPFISelDag(BPFTargetMachine &TM) { - return new BPFDAGToDAGISelLegacy(TM); + return new BPFDAGToDAGISel(TM); } diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 7b73c9f..a7bed69 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -48,7 +48,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() { initializeGlobalISel(PR); initializeBPFCheckAndAdjustIRPass(PR); initializeBPFMIPeepholePass(PR); - initializeBPFDAGToDAGISelLegacyPass(PR); + initializeBPFDAGToDAGISelPass(PR); } // DataLayout: little or big endian diff --git a/llvm/lib/Target/CSKY/CSKY.h b/llvm/lib/Target/CSKY/CSKY.h index 21ebf13..7ca630c 100644 --- a/llvm/lib/Target/CSKY/CSKY.h +++ b/llvm/lib/Target/CSKY/CSKY.h @@ -27,7 +27,7 @@ FunctionPass *createCSKYISelDag(CSKYTargetMachine &TM, FunctionPass *createCSKYConstantIslandPass(); void initializeCSKYConstantIslandsPass(PassRegistry &); -void initializeCSKYDAGToDAGISelLegacyPass(PassRegistry &); +void initializeCSKYDAGToDAGISelPass(PassRegistry &); } // namespace llvm diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp index 22da80b..c0c23a45 100644 --- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp +++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp @@ -28,8 +28,10 @@ class CSKYDAGToDAGISel : public SelectionDAGISel { const CSKYSubtarget *Subtarget; public: + static char ID; + explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. @@ -52,20 +54,11 @@ public: #include "CSKYGenDAGISel.inc" }; - -class CSKYDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit CSKYDAGToDAGISelLegacy(CSKYTargetMachine &TM, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<CSKYDAGToDAGISel>(TM, OptLevel)) {} -}; } // namespace -char CSKYDAGToDAGISelLegacy::ID = 0; +char CSKYDAGToDAGISel::ID = 0; -INITIALIZE_PASS(CSKYDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) void CSKYDAGToDAGISel::Select(SDNode *N) { // If we have a custom node, we have already selected @@ -408,5 +401,5 @@ bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand( FunctionPass *llvm::createCSKYISelDag(CSKYTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new CSKYDAGToDAGISelLegacy(TM, OptLevel); + return new CSKYDAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp index a756061..0bbfabe 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp @@ -30,7 +30,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTarget() { PassRegistry *Registry = PassRegistry::getPassRegistry(); initializeCSKYConstantIslandsPass(*Registry); - initializeCSKYDAGToDAGISelLegacyPass(*Registry); + initializeCSKYDAGToDAGISelPass(*Registry); } static std::string computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h index 4a290c7..861f61a 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.h +++ b/llvm/lib/Target/Hexagon/Hexagon.h @@ -22,7 +22,7 @@ namespace llvm { /// Creates a Hexagon-specific Target Transformation Info pass. ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM); - void initializeHexagonDAGToDAGISelLegacyPass(PassRegistry &); + void initializeHexagonDAGToDAGISelPass(PassRegistry &); } // end namespace llvm; #endif diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index febbc95..6fe3fe0 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -60,18 +60,13 @@ namespace llvm { /// Hexagon-specific DAG, ready for instruction scheduling. FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new HexagonDAGToDAGISelLegacy(TM, OptLevel); + return new HexagonDAGToDAGISel(TM, OptLevel); } } -HexagonDAGToDAGISelLegacy::HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<HexagonDAGToDAGISel>(tm, OptLevel)) {} +char HexagonDAGToDAGISel::ID = 0; -char HexagonDAGToDAGISelLegacy::ID = 0; - -INITIALIZE_PASS(HexagonDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(HexagonDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { SDValue Chain = LD->getChain(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index 2d23aee..50162b1 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -29,13 +29,14 @@ class HexagonDAGToDAGISel : public SelectionDAGISel { const HexagonSubtarget *HST; const HexagonInstrInfo *HII; const HexagonRegisterInfo *HRI; - public: + static char ID; + HexagonDAGToDAGISel() = delete; explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr), + : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr), HRI(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { @@ -161,13 +162,6 @@ private: SDValue balanceSubTree(SDNode *N, bool Factorize = false); void rebalanceAddressTrees(); }; // end HexagonDAGToDAGISel - -class HexagonDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm, - CodeGenOptLevel OptLevel); -}; } #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index e488650..3a792ec 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -254,7 +254,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() { initializeHexagonVectorCombineLegacyPass(PR); initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR); initializeHexagonVExtractPass(PR); - initializeHexagonDAGToDAGISelLegacyPass(PR); + initializeHexagonDAGToDAGISelPass(PR); } HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, diff --git a/llvm/lib/Target/Lanai/Lanai.h b/llvm/lib/Target/Lanai/Lanai.h index 72a7efc..0f87b17 100644 --- a/llvm/lib/Target/Lanai/Lanai.h +++ b/llvm/lib/Target/Lanai/Lanai.h @@ -37,7 +37,7 @@ FunctionPass *createLanaiMemAluCombinerPass(); // operations. FunctionPass *createLanaiSetflagAluCombinerPass(); -void initializeLanaiDAGToDAGISelLegacyPass(PassRegistry &); +void initializeLanaiDAGToDAGISelPass(PassRegistry &); } // namespace llvm diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp index af64e2b..6f5495a 100644 --- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -48,10 +48,16 @@ namespace { class LanaiDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + LanaiDAGToDAGISel() = delete; explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine) - : SelectionDAGISel(TargetMachine) {} + : SelectionDAGISel(ID, TargetMachine) {} + + bool runOnMachineFunction(MachineFunction &MF) override { + return SelectionDAGISel::runOnMachineFunction(MF); + } bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode, @@ -91,18 +97,11 @@ bool canBeRepresentedAsSls(const ConstantSDNode &CN) { return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0); } -class LanaiDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit LanaiDAGToDAGISelLegacy(LanaiTargetMachine &TM) - : SelectionDAGISelLegacy(ID, std::make_unique<LanaiDAGToDAGISel>(TM)) {} -}; - } // namespace -char LanaiDAGToDAGISelLegacy::ID = 0; +char LanaiDAGToDAGISel::ID = 0; -INITIALIZE_PASS(LanaiDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(LanaiDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) // Helper functions for ComplexPattern used on LanaiInstrInfo // Used on Lanai Load/Store instructions. @@ -367,5 +366,5 @@ void LanaiDAGToDAGISel::selectFrameIndex(SDNode *Node) { // createLanaiISelDag - This pass converts a legalized DAG into a // Lanai-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createLanaiISelDag(LanaiTargetMachine &TM) { - return new LanaiDAGToDAGISelLegacy(TM); + return new LanaiDAGToDAGISel(TM); } diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index 68eb12f..2357221 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -37,7 +37,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget() { RegisterTargetMachine<LanaiTargetMachine> registered_target( getTheLanaiTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeLanaiDAGToDAGISelLegacyPass(PR); + initializeLanaiDAGToDAGISelPass(PR); } static std::string computeDataLayout() { diff --git a/llvm/lib/Target/LoongArch/LoongArch.h b/llvm/lib/Target/LoongArch/LoongArch.h index 0928ea3..2109176 100644 --- a/llvm/lib/Target/LoongArch/LoongArch.h +++ b/llvm/lib/Target/LoongArch/LoongArch.h @@ -38,7 +38,7 @@ FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM); FunctionPass *createLoongArchOptWInstrsPass(); FunctionPass *createLoongArchPreRAExpandPseudoPass(); FunctionPass *createLoongArchExpandPseudoPass(); -void initializeLoongArchDAGToDAGISelLegacyPass(PassRegistry &); +void initializeLoongArchDAGToDAGISelPass(PassRegistry &); void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &); void initializeLoongArchOptWInstrsPass(PassRegistry &); void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &); diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp index b6ade6b..726856b 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp @@ -22,14 +22,9 @@ using namespace llvm; #define DEBUG_TYPE "loongarch-isel" #define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection" -char LoongArchDAGToDAGISelLegacy::ID; +char LoongArchDAGToDAGISel::ID; -LoongArchDAGToDAGISelLegacy::LoongArchDAGToDAGISelLegacy( - LoongArchTargetMachine &TM) - : SelectionDAGISelLegacy(ID, std::make_unique<LoongArchDAGToDAGISel>(TM)) {} - -INITIALIZE_PASS(LoongArchDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, - false) +INITIALIZE_PASS(LoongArchDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) void LoongArchDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we have already selected. @@ -419,5 +414,5 @@ bool LoongArchDAGToDAGISel::selectVSplatUimmPow2(SDValue N, // This pass converts a legalized DAG into a LoongArch-specific DAG, ready // for instruction scheduling. FunctionPass *llvm::createLoongArchISelDag(LoongArchTargetMachine &TM) { - return new LoongArchDAGToDAGISelLegacy(TM); + return new LoongArchDAGToDAGISel(TM); } diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h index 363b4f0..48a178b 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h @@ -24,10 +24,12 @@ class LoongArchDAGToDAGISel : public SelectionDAGISel { const LoongArchSubtarget *Subtarget = nullptr; public: + static char ID; + LoongArchDAGToDAGISel() = delete; explicit LoongArchDAGToDAGISel(LoongArchTargetMachine &TM) - : SelectionDAGISel(TM) {} + : SelectionDAGISel(ID, TM) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<LoongArchSubtarget>(); @@ -67,12 +69,6 @@ public: #include "LoongArchGenDAGISel.inc" }; -class LoongArchDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit LoongArchDAGToDAGISelLegacy(LoongArchTargetMachine &TM); -}; - } // end namespace llvm #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp index 83466d5..2b2d4e4 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp @@ -36,7 +36,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTarget() { auto *PR = PassRegistry::getPassRegistry(); initializeLoongArchOptWInstrsPass(*PR); initializeLoongArchPreRAExpandPseudoPass(*PR); - initializeLoongArchDAGToDAGISelLegacyPass(*PR); + initializeLoongArchDAGToDAGISelPass(*PR); } static cl::opt<bool> diff --git a/llvm/lib/Target/M68k/M68k.h b/llvm/lib/Target/M68k/M68k.h index 5db9d79..1d0f383 100644 --- a/llvm/lib/Target/M68k/M68k.h +++ b/llvm/lib/Target/M68k/M68k.h @@ -46,7 +46,7 @@ InstructionSelector * createM68kInstructionSelector(const M68kTargetMachine &, const M68kSubtarget &, const M68kRegisterBankInfo &); -void initializeM68kDAGToDAGISelLegacyPass(PassRegistry &); +void initializeM68kDAGToDAGISelPass(PassRegistry &); void initializeM68kExpandPseudoPass(PassRegistry &); void initializeM68kGlobalBaseRegPass(PassRegistry &); void initializeM68kCollapseMOVEMPass(PassRegistry &); diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp index dc89fec..e3aa9cb 100644 --- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp +++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp @@ -174,10 +174,12 @@ namespace { class M68kDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + M68kDAGToDAGISel() = delete; explicit M68kDAGToDAGISel(M68kTargetMachine &TM) - : SelectionDAGISel(TM), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override; bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override; @@ -314,18 +316,11 @@ private: SDNode *getGlobalBaseReg(); }; -class M68kDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit M68kDAGToDAGISelLegacy(M68kTargetMachine &TM) - : SelectionDAGISelLegacy(ID, std::make_unique<M68kDAGToDAGISel>(TM)) {} -}; - -char M68kDAGToDAGISelLegacy::ID; +char M68kDAGToDAGISel::ID; } // namespace -INITIALIZE_PASS(M68kDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(M68kDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { @@ -362,7 +357,7 @@ bool M68kDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { /// This pass converts a legalized DAG into a M68k-specific DAG, /// ready for instruction scheduling. FunctionPass *llvm::createM68kISelDag(M68kTargetMachine &TM) { - return new M68kDAGToDAGISelLegacy(TM); + return new M68kDAGToDAGISel(TM); } static bool doesDispFitFI(M68kISelAddressMode &AM) { diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp index b65de5e..bbbcb15 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp +++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp @@ -37,7 +37,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTarget() { RegisterTargetMachine<M68kTargetMachine> X(getTheM68kTarget()); auto *PR = PassRegistry::getPassRegistry(); initializeGlobalISel(*PR); - initializeM68kDAGToDAGISelLegacyPass(*PR); + initializeM68kDAGToDAGISelPass(*PR); initializeM68kExpandPseudoPass(*PR); initializeM68kGlobalBaseRegPass(*PR); initializeM68kCollapseMOVEMPass(*PR); diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h index 0198359..60685b6 100644 --- a/llvm/lib/Target/MSP430/MSP430.h +++ b/llvm/lib/Target/MSP430/MSP430.h @@ -43,7 +43,7 @@ FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, FunctionPass *createMSP430BranchSelectionPass(); -void initializeMSP430DAGToDAGISelLegacyPass(PassRegistry &); +void initializeMSP430DAGToDAGISelPass(PassRegistry &); } // namespace llvm diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 7be51d9..efb23b1 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -91,10 +91,12 @@ namespace { namespace { class MSP430DAGToDAGISel : public SelectionDAGISel { public: + static char ID; + MSP430DAGToDAGISel() = delete; MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} private: bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); @@ -117,26 +119,18 @@ namespace { bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp); }; - - class MSP430DAGToDAGISelLegacy : public SelectionDAGISelLegacy { - public: - static char ID; - MSP430DAGToDAGISelLegacy(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<MSP430DAGToDAGISel>(TM, OptLevel)) {} - }; } // end anonymous namespace -char MSP430DAGToDAGISelLegacy::ID; +char MSP430DAGToDAGISel::ID; -INITIALIZE_PASS(MSP430DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(MSP430DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) /// createMSP430ISelDag - This pass converts a legalized DAG into a /// MSP430-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new MSP430DAGToDAGISelLegacy(TM, OptLevel); + return new MSP430DAGToDAGISel(TM, OptLevel); } /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode. diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index f307c37..ed0fcf7 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -26,7 +26,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() { // Register the target. RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeMSP430DAGToDAGISelLegacyPass(PR); + initializeMSP430DAGToDAGISelPass(PR); } static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) { diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h index 36a1733..f0cf039 100644 --- a/llvm/lib/Target/Mips/Mips.h +++ b/llvm/lib/Target/Mips/Mips.h @@ -47,7 +47,7 @@ InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &, void initializeMicroMipsSizeReducePass(PassRegistry &); void initializeMipsBranchExpansionPass(PassRegistry &); -void initializeMipsDAGToDAGISelLegacyPass(PassRegistry &); +void initializeMipsDAGToDAGISelPass(PassRegistry &); void initializeMipsDelaySlotFillerPass(PassRegistry &); void initializeMipsMulMulBugFixPass(PassRegistry &); void initializeMipsPostLegalizerCombinerPass(PassRegistry &); diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index b8e6dce..0be9b94 100644 --- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -219,11 +219,7 @@ bool Mips16DAGToDAGISel::trySelect(SDNode *Node) { return false; } -Mips16DAGToDAGISelLegacy::Mips16DAGToDAGISelLegacy(MipsTargetMachine &TM, - CodeGenOptLevel OL) - : MipsDAGToDAGISelLegacy(std::make_unique<Mips16DAGToDAGISel>(TM, OL)) {} - FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new Mips16DAGToDAGISelLegacy(TM, OptLevel); + return new Mips16DAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h index ec6e745..c6d3bde 100644 --- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h @@ -47,11 +47,6 @@ private: void initMips16SPAliasReg(MachineFunction &MF); }; -class Mips16DAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy { -public: - explicit Mips16DAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL); -}; - FunctionPass *createMips16ISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel); } diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index f6f32fd..01b41f3 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -49,11 +49,11 @@ using namespace llvm; // instructions for SelectionDAG operations. //===----------------------------------------------------------------------===// -void MipsDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const { +void MipsDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { // There are multiple MipsDAGToDAGISel instances added to the pass pipeline. // We need to preserve StackProtector for the next one. AU.addPreserved<StackProtector>(); - SelectionDAGISelLegacy::getAnalysisUsage(AU); + SelectionDAGISel::getAnalysisUsage(AU); } bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { @@ -344,10 +344,6 @@ bool MipsDAGToDAGISel::isUnneededShiftMask(SDNode *N, return (Known.Zero | RHS).countr_one() >= ShAmtBits; } -char MipsDAGToDAGISelLegacy::ID = 0; +char MipsDAGToDAGISel::ID = 0; -MipsDAGToDAGISelLegacy::MipsDAGToDAGISelLegacy( - std::unique_ptr<SelectionDAGISel> S) - : SelectionDAGISelLegacy(ID, std::move(S)) {} - -INITIALIZE_PASS(MipsDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(MipsDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h index 6135f96..52207d0 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h @@ -30,13 +30,17 @@ namespace llvm { class MipsDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + MipsDAGToDAGISel() = delete; explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) - : SelectionDAGISel(TM, OL), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override; + void getAnalysisUsage(AnalysisUsage &AU) const override; + protected: SDNode *getGlobalBaseReg(); @@ -141,13 +145,6 @@ private: std::vector<SDValue> &OutOps) override; bool isUnneededShiftMask(SDNode *N, unsigned ShAmtBits) const; }; - -class MipsDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - MipsDAGToDAGISelLegacy(std::unique_ptr<SelectionDAGISel> S); - void getAnalysisUsage(AnalysisUsage &AU) const override; -}; } #endif diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 7ad300c..ab39d1b 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -44,9 +44,9 @@ bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { return MipsDAGToDAGISel::runOnMachineFunction(MF); } -void MipsSEDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const { +void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<DominatorTreeWrapperPass>(); - SelectionDAGISelLegacy::getAnalysisUsage(AU); + SelectionDAGISel::getAnalysisUsage(AU); } void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, @@ -1439,11 +1439,7 @@ bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand( return true; } -MipsSEDAGToDAGISelLegacy::MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM, - CodeGenOptLevel OL) - : MipsDAGToDAGISelLegacy(std::make_unique<MipsSEDAGToDAGISel>(TM, OL)) {} - FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new MipsSEDAGToDAGISelLegacy(TM, OptLevel); + return new MipsSEDAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h index 7b843b0..96dc876 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h @@ -27,6 +27,8 @@ private: bool runOnMachineFunction(MachineFunction &MF) override; + void getAnalysisUsage(AnalysisUsage &AU) const override; + void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, MachineFunction &MF); @@ -137,12 +139,6 @@ private: std::vector<SDValue> &OutOps) override; }; -class MipsSEDAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy { -public: - explicit MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL); - void getAnalysisUsage(AnalysisUsage &AU) const override; -}; - FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel); } diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 9515e50..4c4bf70 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -67,7 +67,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { initializeMipsPreLegalizerCombinerPass(*PR); initializeMipsPostLegalizerCombinerPass(*PR); initializeMipsMulMulBugFixPass(*PR); - initializeMipsDAGToDAGISelLegacyPass(*PR); + initializeMipsDAGToDAGISelPass(*PR); } static std::string computeDataLayout(const Triple &TT, StringRef CPU, diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h index 5eefab5..07ee349 100644 --- a/llvm/lib/Target/NVPTX/NVPTX.h +++ b/llvm/lib/Target/NVPTX/NVPTX.h @@ -194,7 +194,7 @@ enum PrmtMode { }; } } -void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &); +void initializeNVPTXDAGToDAGISelPass(PassRegistry &); } // namespace llvm // Defines symbolic names for NVPTX registers. This defines a mapping from diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index 1e1cbb1..2713b68 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -38,21 +38,16 @@ static cl::opt<bool> /// NVPTX-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOptLevel OptLevel) { - return new NVPTXDAGToDAGISelLegacy(TM, OptLevel); + return new NVPTXDAGToDAGISel(TM, OptLevel); } -NVPTXDAGToDAGISelLegacy::NVPTXDAGToDAGISelLegacy(NVPTXTargetMachine &tm, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<NVPTXDAGToDAGISel>(tm, OptLevel)) {} +char NVPTXDAGToDAGISel::ID = 0; -char NVPTXDAGToDAGISelLegacy::ID = 0; - -INITIALIZE_PASS(NVPTXDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(tm, OptLevel), TM(tm) { + : SelectionDAGISel(ID, tm, OptLevel), TM(tm) { doMulWide = (OptLevel > CodeGenOptLevel::None); } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h index c552435..7a77747 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h @@ -39,6 +39,8 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel { bool doRsqrtOpt() const; public: + static char ID; + NVPTXDAGToDAGISel() = delete; explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOptLevel OptLevel); @@ -99,13 +101,6 @@ private: static unsigned GetConvertOpcode(MVT DestTy, MVT SrcTy, LoadSDNode *N); }; - -class NVPTXDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit NVPTXDAGToDAGISelLegacy(NVPTXTargetMachine &tm, - CodeGenOptLevel OptLevel); -}; } // end namespace llvm #endif diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 4dc3cea..2a47c16 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -103,7 +103,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() { initializeNVPTXCtorDtorLoweringLegacyPass(PR); initializeNVPTXLowerAggrCopiesPass(PR); initializeNVPTXProxyRegErasurePass(PR); - initializeNVPTXDAGToDAGISelLegacyPass(PR); + initializeNVPTXDAGToDAGISelPass(PR); initializeNVPTXAAWrapperPassPass(PR); initializeNVPTXExternalAAWrapperPass(PR); } diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index 94a59d1..eb8886d 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -78,7 +78,7 @@ class ModulePass; void initializePPCMIPeepholePass(PassRegistry&); void initializePPCExpandAtomicPseudoPass(PassRegistry &); void initializePPCCTRLoopsPass(PassRegistry &); - void initializePPCDAGToDAGISelLegacyPass(PassRegistry &); + void initializePPCDAGToDAGISelPass(PassRegistry &); void initializePPCMergeStringPoolPass(PassRegistry &); extern char &PPCVSXFMAMutateID; diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 275b333..26560dc 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -147,10 +147,12 @@ namespace { unsigned GlobalBaseReg = 0; public: + static char ID; + PPCDAGToDAGISel() = delete; explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(tm, OptLevel), TM(tm) {} + : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {} bool runOnMachineFunction(MachineFunction &MF) override { // Make sure we re-emit a set of the global base reg if necessary @@ -445,19 +447,11 @@ private: void transferMemOperands(SDNode *N, SDNode *Result); }; - class PPCDAGToDAGISelLegacy : public SelectionDAGISelLegacy { - public: - static char ID; - explicit PPCDAGToDAGISelLegacy(PPCTargetMachine &tm, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<PPCDAGToDAGISel>(tm, OptLevel)) {} - }; } // end anonymous namespace -char PPCDAGToDAGISelLegacy::ID = 0; +char PPCDAGToDAGISel::ID = 0; -INITIALIZE_PASS(PPCDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(PPCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. @@ -7927,5 +7921,5 @@ void PPCDAGToDAGISel::PeepholePPC64() { /// FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new PPCDAGToDAGISelLegacy(TM, OptLevel); + return new PPCDAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 1ef891d..714cf69 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -141,7 +141,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() { initializePPCExpandAtomicPseudoPass(PR); initializeGlobalISel(PR); initializePPCCTRLoopsPass(PR); - initializePPCDAGToDAGISelLegacyPass(PR); + initializePPCDAGToDAGISelPass(PR); initializePPCMergeStringPoolPass(PR); } diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h index 8d2e1fc..dcf4c65 100644 --- a/llvm/lib/Target/RISCV/RISCV.h +++ b/llvm/lib/Target/RISCV/RISCV.h @@ -82,7 +82,7 @@ void initializeRISCVPushPopOptPass(PassRegistry &); InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &); -void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &); +void initializeRISCVDAGToDAGISelPass(PassRegistry &); FunctionPass *createRISCVPostLegalizerCombiner(); void initializeRISCVPostLegalizerCombinerPass(PassRegistry &); diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 251401d..d965dd4 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -3912,14 +3912,9 @@ bool RISCVDAGToDAGISel::doPeepholeNoRegPassThru() { // for instruction scheduling. FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new RISCVDAGToDAGISelLegacy(TM, OptLevel); + return new RISCVDAGToDAGISel(TM, OptLevel); } -char RISCVDAGToDAGISelLegacy::ID = 0; +char RISCVDAGToDAGISel::ID = 0; -RISCVDAGToDAGISelLegacy::RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TM, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<RISCVDAGToDAGISel>(TM, OptLevel)) {} - -INITIALIZE_PASS(RISCVDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index 5d70245..ece04dd 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -25,11 +25,13 @@ class RISCVDAGToDAGISel : public SelectionDAGISel { const RISCVSubtarget *Subtarget = nullptr; public: + static char ID; + RISCVDAGToDAGISel() = delete; explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TargetMachine, OptLevel) {} + : SelectionDAGISel(ID, TargetMachine, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<RISCVSubtarget>(); @@ -194,13 +196,6 @@ private: bool performCombineVMergeAndVOps(SDNode *N); }; -class RISCVDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TargetMachine, - CodeGenOptLevel OptLevel); -}; - namespace RISCV { struct VLSEGPseudo { uint16_t NF : 4; diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 35d0b34..87ae2ee 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -123,7 +123,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { initializeRISCVInsertVSETVLIPass(*PR); initializeRISCVInsertReadWriteCSRPass(*PR); initializeRISCVInsertWriteVXRMPass(*PR); - initializeRISCVDAGToDAGISelLegacyPass(*PR); + initializeRISCVDAGToDAGISelPass(*PR); initializeRISCVMoveMergePass(*PR); initializeRISCVPushPopOptPass(*PR); } diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h index 33a8034..fca7657 100644 --- a/llvm/lib/Target/Sparc/Sparc.h +++ b/llvm/lib/Target/Sparc/Sparc.h @@ -31,7 +31,7 @@ FunctionPass *createSparcDelaySlotFillerPass(); void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); -void initializeSparcDAGToDAGISelLegacyPass(PassRegistry &); +void initializeSparcDAGToDAGISelPass(PassRegistry &); } // namespace llvm namespace llvm { diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 2531611..3c9841d 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -35,11 +35,12 @@ class SparcDAGToDAGISel : public SelectionDAGISel { /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can /// make the right decision when generating code for different targets. const SparcSubtarget *Subtarget = nullptr; - public: + static char ID; + SparcDAGToDAGISel() = delete; - explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {} + explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<SparcSubtarget>(); @@ -65,18 +66,11 @@ private: SDNode* getGlobalBaseReg(); bool tryInlineAsm(SDNode *N); }; - -class SparcDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit SparcDAGToDAGISelLegacy(SparcTargetMachine &tm) - : SelectionDAGISelLegacy(ID, std::make_unique<SparcDAGToDAGISel>(tm)) {} -}; } // end anonymous namespace -char SparcDAGToDAGISelLegacy::ID = 0; +char SparcDAGToDAGISel::ID = 0; -INITIALIZE_PASS(SparcDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(SparcDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) SDNode* SparcDAGToDAGISel::getGlobalBaseReg() { Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); @@ -403,5 +397,5 @@ bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand( /// SPARC-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) { - return new SparcDAGToDAGISelLegacy(TM); + return new SparcDAGToDAGISel(TM); } diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index ea40323..20ddafb0 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -28,7 +28,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeSparcDAGToDAGISelLegacyPass(PR); + initializeSparcDAGToDAGISelPass(PR); } static cl::opt<bool> diff --git a/llvm/lib/Target/SystemZ/SystemZ.h b/llvm/lib/Target/SystemZ/SystemZ.h index 8824954..d7aa9e4 100644 --- a/llvm/lib/Target/SystemZ/SystemZ.h +++ b/llvm/lib/Target/SystemZ/SystemZ.h @@ -199,7 +199,7 @@ FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM); FunctionPass *createSystemZTDCPass(); void initializeSystemZCopyPhysRegsPass(PassRegistry &); -void initializeSystemZDAGToDAGISelLegacyPass(PassRegistry &); +void initializeSystemZDAGToDAGISelPass(PassRegistry &); void initializeSystemZElimComparePass(PassRegistry &); void initializeSystemZLDCleanupPass(PassRegistry &); void initializeSystemZLongBranchPass(PassRegistry &); diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 6c6a9b4..1bf23c2 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -356,10 +356,12 @@ class SystemZDAGToDAGISel : public SelectionDAGISel { bool shouldSelectForReassoc(SDNode *N) const; public: + static char ID; + SystemZDAGToDAGISel() = delete; SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { const Function &F = MF.getFunction(); @@ -385,24 +387,15 @@ public: // Include the pieces autogenerated from the target description. #include "SystemZGenDAGISel.inc" }; - -class SystemZDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit SystemZDAGToDAGISelLegacy(SystemZTargetMachine &TM, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<SystemZDAGToDAGISel>(TM, OptLevel)) {} -}; } // end anonymous namespace -char SystemZDAGToDAGISelLegacy::ID = 0; +char SystemZDAGToDAGISel::ID = 0; -INITIALIZE_PASS(SystemZDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(SystemZDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new SystemZDAGToDAGISelLegacy(TM, OptLevel); + return new SystemZDAGToDAGISel(TM, OptLevel); } // Return true if Val should be selected as a displacement for an address diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index 6f76839..dced64d 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -47,7 +47,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() { initializeSystemZShortenInstPass(PR); initializeSystemZPostRewritePass(PR); initializeSystemZTDCPassPass(PR); - initializeSystemZDAGToDAGISelLegacyPass(PR); + initializeSystemZDAGToDAGISelPass(PR); } static std::string computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/VE/VE.h b/llvm/lib/Target/VE/VE.h index ee76c51..6f024301 100644 --- a/llvm/lib/Target/VE/VE.h +++ b/llvm/lib/Target/VE/VE.h @@ -29,7 +29,7 @@ class VETargetMachine; FunctionPass *createVEISelDag(VETargetMachine &TM); FunctionPass *createLVLGenPass(); -void initializeVEDAGToDAGISelLegacyPass(PassRegistry &); +void initializeVEDAGToDAGISelPass(PassRegistry &); void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp index 680bd12..87646bc 100644 --- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp +++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp @@ -34,9 +34,11 @@ class VEDAGToDAGISel : public SelectionDAGISel { const VESubtarget *Subtarget; public: + static char ID; + VEDAGToDAGISel() = delete; - explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {} + explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<VESubtarget>(); @@ -68,18 +70,11 @@ private: bool matchADDRrr(SDValue N, SDValue &Base, SDValue &Index); bool matchADDRri(SDValue N, SDValue &Base, SDValue &Offset); }; - -class VEDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit VEDAGToDAGISelLegacy(VETargetMachine &tm) - : SelectionDAGISelLegacy(ID, std::make_unique<VEDAGToDAGISel>(tm)) {} -}; } // end anonymous namespace -char VEDAGToDAGISelLegacy::ID = 0; +char VEDAGToDAGISel::ID = 0; -INITIALIZE_PASS(VEDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(VEDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Offset) { @@ -341,5 +336,5 @@ SDNode *VEDAGToDAGISel::getGlobalBaseReg() { /// VE-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) { - return new VEDAGToDAGISelLegacy(TM); + return new VEDAGToDAGISel(TM); } diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp index 383667b..6f4e137 100644 --- a/llvm/lib/Target/VE/VETargetMachine.cpp +++ b/llvm/lib/Target/VE/VETargetMachine.cpp @@ -30,7 +30,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() { RegisterTargetMachine<VETargetMachine> X(getTheVETarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeVEDAGToDAGISelLegacyPass(PR); + initializeVEDAGToDAGISelPass(PR); } static std::string computeDataLayout(const Triple &T) { diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h index 8f142fa..7fc8546 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.h +++ b/llvm/lib/Target/WebAssembly/WebAssembly.h @@ -67,7 +67,7 @@ void initializeWebAssemblyArgumentMovePass(PassRegistry &); void initializeWebAssemblyCleanCodeAfterTrapPass(PassRegistry &); void initializeWebAssemblyCFGSortPass(PassRegistry &); void initializeWebAssemblyCFGStackifyPass(PassRegistry &); -void initializeWebAssemblyDAGToDAGISelLegacyPass(PassRegistry &); +void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &); void initializeWebAssemblyDebugFixupPass(PassRegistry &); void initializeWebAssemblyExceptionInfoPass(PassRegistry &); void initializeWebAssemblyExplicitLocalsPass(PassRegistry &); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp index 0f06f54..8833aee 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp @@ -42,11 +42,13 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel { const WebAssemblySubtarget *Subtarget; public: + static char ID; + WebAssemblyDAGToDAGISel() = delete; WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n" @@ -80,21 +82,11 @@ private: bool SelectAddrAddOperands(MVT OffsetType, SDValue N, SDValue &Offset, SDValue &Addr); }; - -class WebAssemblyDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - explicit WebAssemblyDAGToDAGISelLegacy(WebAssemblyTargetMachine &TM, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<WebAssemblyDAGToDAGISel>(TM, OptLevel)) {} -}; } // end anonymous namespace -char WebAssemblyDAGToDAGISelLegacy::ID; +char WebAssemblyDAGToDAGISel::ID; -INITIALIZE_PASS(WebAssemblyDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, - false) +INITIALIZE_PASS(WebAssemblyDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) void WebAssemblyDAGToDAGISel::PreprocessISelDAG() { // Stack objects that should be allocated to locals are hoisted to WebAssembly @@ -417,5 +409,5 @@ bool WebAssemblyDAGToDAGISel::SelectAddrOperands64(SDValue Op, SDValue &Offset, /// for instruction scheduling. FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new WebAssemblyDAGToDAGISelLegacy(TM, OptLevel); + return new WebAssemblyDAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 23539a5..fd92a35 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -90,7 +90,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget() { initializeWebAssemblyMCLowerPrePassPass(PR); initializeWebAssemblyLowerRefTypesIntPtrConvPass(PR); initializeWebAssemblyFixBrTableDefaultsPass(PR); - initializeWebAssemblyDAGToDAGISelLegacyPass(PR); + initializeWebAssemblyDAGToDAGISelPass(PR); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h index fdb9e4c..21623a8 100644 --- a/llvm/lib/Target/X86/X86.h +++ b/llvm/lib/Target/X86/X86.h @@ -179,7 +179,7 @@ void initializeX86AvoidSFBPassPass(PassRegistry &); void initializeX86AvoidTrailingCallPassPass(PassRegistry &); void initializeX86CallFrameOptimizationPass(PassRegistry &); void initializeX86CmovConverterPassPass(PassRegistry &); -void initializeX86DAGToDAGISelLegacyPass(PassRegistry &); +void initializeX86DAGToDAGISelPass(PassRegistry &); void initializeX86DomainReassignmentPass(PassRegistry &); void initializeX86ExecutionDomainFixPass(PassRegistry &); void initializeX86ExpandPseudoPass(PassRegistry &); diff --git a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp index cc5937d..7c1fb0b 100644 --- a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp +++ b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp @@ -10,12 +10,10 @@ /// TODO: Port CodeGen passes to new pass manager. //===----------------------------------------------------------------------===// -#include "X86ISelDAGToDAG.h" #include "X86TargetMachine.h" #include "llvm/MC/MCStreamer.h" #include "llvm/Passes/CodeGenPassBuilder.h" -#include "llvm/Passes/PassBuilder.h" using namespace llvm; @@ -42,20 +40,13 @@ void X86CodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass, // TODO: Add AsmPrinter. } -Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const { +Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &) const { // TODO: Add instruction selector. - addPass(X86ISelDAGToDAGPass(static_cast<X86TargetMachine &>(TM))); return Error::success(); } } // namespace -void X86TargetMachine::registerPassBuilderCallbacks( - PassBuilder &PB, bool PopulateClassToPassNames) { -#define GET_PASS_REGISTRY "X86PassRegistry.def" -#include "llvm/Passes/TargetPassRegistry.inc" -} - Error X86TargetMachine::buildCodeGenPipeline( ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, const CGPassBuilderOption &Opt, diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 0bf3294..3227bf7 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -11,7 +11,6 @@ // //===----------------------------------------------------------------------===// -#include "X86ISelDAGToDAG.h" #include "X86.h" #include "X86MachineFunctionInfo.h" #include "X86RegisterInfo.h" @@ -170,10 +169,12 @@ namespace { bool IndirectTlsSegRefs; public: + static char ID; + X86DAGToDAGISel() = delete; explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr), + : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr), OptForMinSize(false), IndirectTlsSegRefs(false) {} bool runOnMachineFunction(MachineFunction &MF) override { @@ -186,7 +187,9 @@ namespace { OptForMinSize = MF.getFunction().hasMinSize(); assert((!OptForMinSize || MF.getFunction().hasOptSize()) && "OptForMinSize implies OptForSize"); - return SelectionDAGISel::runOnMachineFunction(MF); + + SelectionDAGISel::runOnMachineFunction(MF); + return true; } void emitFunctionEntryCode() override; @@ -574,20 +577,11 @@ namespace { bool hasNoSignFlagUses(SDValue Flags) const; bool hasNoCarryFlagUses(SDValue Flags) const; }; - - class X86DAGToDAGISelLegacy : public SelectionDAGISelLegacy { - public: - static char ID; - explicit X86DAGToDAGISelLegacy(X86TargetMachine &tm, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<X86DAGToDAGISel>(tm, OptLevel)) {} - }; } -char X86DAGToDAGISelLegacy::ID = 0; +char X86DAGToDAGISel::ID = 0; -INITIALIZE_PASS(X86DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(X86DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) // Returns true if this masked compare can be implemented legally with this // type. @@ -6599,13 +6593,9 @@ bool X86DAGToDAGISel::SelectInlineAsmMemoryOperand( return false; } -X86ISelDAGToDAGPass::X86ISelDAGToDAGPass(X86TargetMachine &TM) - : SelectionDAGISelPass( - std::make_unique<X86DAGToDAGISel>(TM, TM.getOptLevel())) {} - /// This pass converts a legalized DAG into a X86-specific DAG, /// ready for instruction scheduling. FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new X86DAGToDAGISelLegacy(TM, OptLevel); + return new X86DAGToDAGISel(TM, OptLevel); } diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.h b/llvm/lib/Target/X86/X86ISelDAGToDAG.h deleted file mode 100644 index 1f30c25b..0000000 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.h +++ /dev/null @@ -1,25 +0,0 @@ -//===-- X86ISelDAGToDAG.h ---------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H -#define LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H - -#include "llvm/CodeGen/SelectionDAGISel.h" - -namespace llvm { - -class X86TargetMachine; - -class X86ISelDAGToDAGPass : public SelectionDAGISelPass { -public: - X86ISelDAGToDAGPass(X86TargetMachine &TM); -}; - -} // namespace llvm - -#endif // LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H diff --git a/llvm/lib/Target/X86/X86PassRegistry.def b/llvm/lib/Target/X86/X86PassRegistry.def deleted file mode 100644 index 620526ff..0000000 --- a/llvm/lib/Target/X86/X86PassRegistry.def +++ /dev/null @@ -1,19 +0,0 @@ -//===- X86PassRegistry.def - Registry of X86 specific passes ----*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file is used as the registry of passes that are part of the X86 backend. -// -//===----------------------------------------------------------------------===// - -// NOTE: NO INCLUDE GUARD DESIRED! - -#ifndef MACHINE_FUNCTION_PASS -#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) -#endif -MACHINE_FUNCTION_PASS("x86-isel", X86ISelDAGToDAGPass(*this)) -#undef MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 27542e5..ab59cf8 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -100,7 +100,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() { initializeX86PartialReductionPass(PR); initializePseudoProbeInserterPass(PR); initializeX86ReturnThunksPass(PR); - initializeX86DAGToDAGISelLegacyPass(PR); + initializeX86DAGToDAGISelPass(PR); initializeX86ArgumentStackSlotPassPass(PR); initializeX86FixupInstTuningPassPass(PR); initializeX86FixupVectorConstantsPassPass(PR); diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 4a5f20f..4e7ded1 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -58,9 +58,6 @@ public: createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override; - void registerPassBuilderCallbacks(PassBuilder &PB, - bool PopulateClassToPassNames) override; - Error buildCodeGenPipeline(ModulePassManager &, raw_pwrite_stream &, raw_pwrite_stream *, CodeGenFileType, const CGPassBuilderOption &, diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h index ad50f05..f019fa4 100644 --- a/llvm/lib/Target/XCore/XCore.h +++ b/llvm/lib/Target/XCore/XCore.h @@ -31,7 +31,7 @@ namespace llvm { FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel); ModulePass *createXCoreLowerThreadLocalPass(); - void initializeXCoreDAGToDAGISelLegacyPass(PassRegistry &); + void initializeXCoreDAGToDAGISelPass(PassRegistry &); } // end namespace llvm; diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp index dcbf114..1535eb6 100644 --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -41,10 +41,12 @@ namespace { class XCoreDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + XCoreDAGToDAGISel() = delete; XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} void Select(SDNode *N) override; bool tryBRIND(SDNode *N); @@ -76,27 +78,18 @@ namespace { // Include the pieces autogenerated from the target description. #include "XCoreGenDAGISel.inc" }; - - class XCoreDAGToDAGISelLegacy : public SelectionDAGISelLegacy { - public: - static char ID; - explicit XCoreDAGToDAGISelLegacy(XCoreTargetMachine &TM, - CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<XCoreDAGToDAGISel>(TM, OptLevel)) {} - }; } // end anonymous namespace -char XCoreDAGToDAGISelLegacy::ID = 0; +char XCoreDAGToDAGISel::ID = 0; -INITIALIZE_PASS(XCoreDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(XCoreDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) /// createXCoreISelDag - This pass converts a legalized DAG into a /// XCore-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new XCoreDAGToDAGISelLegacy(TM, OptLevel); + return new XCoreDAGToDAGISel(TM, OptLevel); } bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index bb5beef..374e91d 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -107,7 +107,7 @@ void XCorePassConfig::addPreEmitPass() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() { RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeXCoreDAGToDAGISelLegacyPass(PR); + initializeXCoreDAGToDAGISelPass(PR); } TargetTransformInfo diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 145f285..5ebedef 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -28,8 +28,14 @@ namespace { class XtensaDAGToDAGISel : public SelectionDAGISel { public: + static char ID; + XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(TM, OptLevel) {} + : SelectionDAGISel(ID, TM, OptLevel) {} + + StringRef getPassName() const override { + return "Xtensa DAG->DAG Pattern Instruction Selection"; + } void Select(SDNode *Node) override; @@ -101,26 +107,13 @@ public: // Include the pieces autogenerated from the target description. #include "XtensaGenDAGISel.inc" }; // namespace - -class XtensaDAGToDAGISelLegacy : public SelectionDAGISelLegacy { -public: - static char ID; - - XtensaDAGToDAGISelLegacy(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISelLegacy( - ID, std::make_unique<XtensaDAGToDAGISel>(TM, OptLevel)) {} - - StringRef getPassName() const override { - return "Xtensa DAG->DAG Pattern Instruction Selection"; - } -}; } // end anonymous namespace -char XtensaDAGToDAGISelLegacy::ID = 0; +char XtensaDAGToDAGISel::ID = 0; FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new XtensaDAGToDAGISelLegacy(TM, OptLevel); + return new XtensaDAGToDAGISel(TM, OptLevel); } void XtensaDAGToDAGISel::Select(SDNode *Node) { |