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| author | Pierre van Houtryve <pierre.vanhoutryve@amd.com> | 2024-02-13 09:07:51 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-13 09:07:51 +0100 |
| commit | 87d771193490e6604f132752438bd8404c83498c (patch) | |
| tree | f83d36eb2288d0b02296155c3451a02a84ad9064 /llvm/lib | |
| parent | a1efe56ace6099959ac97fcb09b9a7837b6d0255 (diff) | |
| download | llvm-87d771193490e6604f132752438bd8404c83498c.zip llvm-87d771193490e6604f132752438bd8404c83498c.tar.gz llvm-87d771193490e6604f132752438bd8404c83498c.tar.bz2 | |
[AMDGPU][SIMemoryLegalizer] Fix order of GL0/1_INV on GFX10/11 (#81450)
Fixes SWDEV-443292
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp index 84b9330..f62e808 100644 --- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -2030,8 +2030,11 @@ bool SIGfx10CacheControl::insertAcquire(MachineBasicBlock::iterator &MI, switch (Scope) { case SIAtomicScope::SYSTEM: case SIAtomicScope::AGENT: - BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV)); + // The order of invalidates matter here. We must invalidate "outer in" + // so L1 -> L0 to avoid L0 pulling in stale data from L1 when it is + // invalidated. BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL1_INV)); + BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV)); Changed = true; break; case SIAtomicScope::WORKGROUP: |