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| author | David Green <david.green@arm.com> | 2024-10-29 21:02:32 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-29 21:02:32 +0000 |
| commit | 83ae171722bea2722afa4efb0558a6d8b8844305 (patch) | |
| tree | d427ea53642691a8de3521309bd89aea041c419c /llvm/lib | |
| parent | 94e7d9c0bfe517507ea08b00fb00c32fb2837a82 (diff) | |
| download | llvm-83ae171722bea2722afa4efb0558a6d8b8844305.zip llvm-83ae171722bea2722afa4efb0558a6d8b8844305.tar.gz llvm-83ae171722bea2722afa4efb0558a6d8b8844305.tar.bz2 | |
[AArch64] Add ComputeNumSignBits for VASHR. (#113957)
As with a normal ISD::SRA node, they take the number of sign bits of the
incoming value and increase it by the shifted amount.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 32ba286..31a720e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2536,6 +2536,11 @@ unsigned AArch64TargetLowering::ComputeNumSignBitsForTargetNode( case AArch64ISD::FCMLTz: // Compares return either 0 or all-ones return VTBits; + case AArch64ISD::VASHR: { + unsigned Tmp = + DAG.ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1); + return std::min<uint64_t>(Tmp + Op.getConstantOperandVal(1), VTBits); + } } return 1; |