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| author | Craig Topper <craig.topper@sifive.com> | 2025-01-08 21:02:46 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-08 21:02:46 -0800 |
| commit | 5d03235c73476dfa3d2dd48c76de106fd1aa2ac7 (patch) | |
| tree | 67ff35649000dfbdac8c42429569ac791dce04cc /llvm/lib | |
| parent | 929b90be30c3a3063e29a94db2079ee4c4f44f0d (diff) | |
| download | llvm-5d03235c73476dfa3d2dd48c76de106fd1aa2ac7.zip llvm-5d03235c73476dfa3d2dd48c76de106fd1aa2ac7.tar.gz llvm-5d03235c73476dfa3d2dd48c76de106fd1aa2ac7.tar.bz2 | |
[RISCV] Add -mcpu=sifive-p550. (#122164)
This is the CPU in SiFive's HiFive Premier P550 development board.
Scheduler model will come in a later patch.
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVProcessors.td | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 61c7c21..6dfed7d 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -321,6 +321,25 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model, [TuneNoSinkSplatOperands, TuneVXRMPipelineFlush])>; +defvar SiFiveP500TuneFeatures = [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneAUIPCADDIFusion, + TunePostRAScheduler]; + +def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb], + SiFiveP500TuneFeatures>; + def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, !listconcat(RVA22U64Features, [FeatureStdExtV, |