[llvm] Use std::size (NFC)

std::size, introduced in C++17, allows us to directly obtain the
number of elements of an array.

11 files changed, 13 insertions, 17 deletions

diff --git a/llvm/lib/IR/Attributes.cpp b/llvm/lib/IR/Attributes.cpp
index a9c4b9f..1a90b94 100644
--- a/llvm/lib/IR/Attributes.cpp
+++ b/llvm/lib/IR/Attributes.cpp
@@ -600,8 +600,7 @@ enum AttributeProperty {
 static bool hasAttributeProperty(Attribute::AttrKind Kind,
                                  AttributeProperty Prop) {
   unsigned Index = Kind - 1;
-  assert(Index < sizeof(AttrPropTable) / sizeof(AttrPropTable[0]) &&
-         "Invalid attribute kind");
+  assert(Index < std::size(AttrPropTable) && "Invalid attribute kind");
   return AttrPropTable[Index] & Prop;
 }
 
diff --git a/llvm/lib/IR/ModuleSummaryIndex.cpp b/llvm/lib/IR/ModuleSummaryIndex.cpp
index 3e82987..2d14407 100644
--- a/llvm/lib/IR/ModuleSummaryIndex.cpp
+++ b/llvm/lib/IR/ModuleSummaryIndex.cpp
@@ -570,8 +570,7 @@ void ModuleSummaryIndex::exportToDot(
         " [color=brown]; // call (hotness : Hot)",
         " [style=bold,color=red]; // call (hotness : Critical)"};
 
-    assert(static_cast<size_t>(TypeOrHotness) <
-           sizeof(EdgeAttrs) / sizeof(EdgeAttrs[0]));
+    assert(static_cast<size_t>(TypeOrHotness) < std::size(EdgeAttrs));
     OS << Pfx << NodeId(SrcMod, SrcId) << " -> " << NodeId(DstMod, DstId)
        << EdgeAttrs[TypeOrHotness] << "\n";
   };
diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp
index de63269..bbea275 100644
--- a/llvm/lib/ProfileData/InstrProfWriter.cpp
+++ b/llvm/lib/ProfileData/InstrProfWriter.cpp
@@ -490,7 +490,7 @@ Error InstrProfWriter::writeImpl(ProfOStream &OS) {
       {CSSummaryOffset, reinterpret_cast<uint64_t *>(TheCSSummary.get()),
        (int)CSSummarySize}};
 
-  OS.patch(PatchItems, sizeof(PatchItems) / sizeof(*PatchItems));
+  OS.patch(PatchItems, std::size(PatchItems));
 
   for (const auto &I : FunctionData)
     for (const auto &F : I.getValue())
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp
index dafbeae..b0099ff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp
@@ -57,8 +57,7 @@ static constexpr const FeatureBitset TargetFeatures = {
 // TODO: Support conservative min/max merging instead of cloning.
 static constexpr const char *AttributeNames[] = {"amdgpu-waves-per-eu"};
 
-static constexpr unsigned NumAttr =
-  sizeof(AttributeNames) / sizeof(AttributeNames[0]);
+static constexpr unsigned NumAttr = std::size(AttributeNames);
 
 class AMDGPUPropagateAttributes {
 
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index 8792ce3..de6ca0a 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -807,7 +807,7 @@ static const uint16_t SysRegDecoderTable[] = {
 static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
                                                uint64_t /*Address*/,
                                                const MCDisassembler *Decoder) {
-  if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0]))
+  if (RegNo >= std::size(SysRegDecoderTable))
     return MCDisassembler::Fail;
 
   if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
@@ -835,7 +835,7 @@ static DecodeStatus
 DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
                              const MCDisassembler *Decoder) {
   RegNo = RegNo >> 1;
-  if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0]))
+  if (RegNo >= std::size(SysReg64DecoderTable))
     return MCDisassembler::Fail;
 
   if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index b80c68e..d5639bd 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -951,8 +951,7 @@ SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
 
   // Assemble multiplication from shift, add, sub using NAF form and running
   // sum.
-  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
-       ++I) {
+  for (unsigned int I = 0; I < std::size(SignedDigit); ++I) {
     if (SignedDigit[I] == 0)
       continue;
 
diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp
index cd67a09..ff792fd 100644
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp
@@ -120,7 +120,7 @@ static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
     return false;
 
   unsigned i;
-  for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
+  for (i = 0; i < std::size(HiRegList); ++i)
     if (HiRegList[i] == Reg)
       break;
 
@@ -149,7 +149,7 @@ static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
     return false;
 
   unsigned i;
-  for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
+  for (i = 0; i < std::size(HiRegList); ++i)
     if (HiRegList[i] == Reg)
       break;
 
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
index 8e46219..cc65b95 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
@@ -222,7 +222,7 @@ void SparcInstPrinter::printMembarTag(const MCInst *MI, int opNum,
   }
 
   bool First = true;
-  for (unsigned i = 0; i < sizeof(TagNames) / sizeof(char *); i++) {
+  for (unsigned i = 0; i < std::size(TagNames); i++) {
     if (Imm & (1 << i)) {
       O << (First ? "" : " | ") << TagNames[i];
       First = false;
diff --git a/llvm/lib/Target/X86/X86CallingConv.cpp b/llvm/lib/Target/X86/X86CallingConv.cpp
index ded93fd..ad61334 100644
--- a/llvm/lib/Target/X86/X86CallingConv.cpp
+++ b/llvm/lib/Target/X86/X86CallingConv.cpp
@@ -240,7 +240,7 @@ static bool CC_X86_32_MCUInReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
   // This is similar to CCAssignToReg<[EAX, EDX, ECX]>, but makes sure
   // not to split i64 and double between a register and stack
   static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX};
-  static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]);
+  static const unsigned NumRegs = std::size(RegList);
 
   SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
 
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index 76f7136..2c0fb35 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -1031,7 +1031,7 @@ unsigned HWAddressSanitizer::retagMask(unsigned AllocaNo) {
                                  48, 16,  120, 248, 56,  24,  8,   124, 252,
                                  60, 28,  12,  4,   126, 254, 62,  30,  14,
                                  6,  2,   127, 63,  31,  15,  7,   3,   1};
-  return FastMasks[AllocaNo % (sizeof(FastMasks) / sizeof(FastMasks[0]))];
+  return FastMasks[AllocaNo % std::size(FastMasks)];
 }
 
 Value *HWAddressSanitizer::applyTagMask(IRBuilder<> &IRB, Value *OldTag) {
diff --git a/llvm/lib/XRay/InstrumentationMap.cpp b/llvm/lib/XRay/InstrumentationMap.cpp
index c60efa4..a68ca19 100644
--- a/llvm/lib/XRay/InstrumentationMap.cpp
+++ b/llvm/lib/XRay/InstrumentationMap.cpp
@@ -188,7 +188,7 @@ loadObj(StringRef Filename, object::OwningBinary<object::ObjectFile> &ObjFile,
         SledEntry::FunctionKinds::TAIL,
         SledEntry::FunctionKinds::LOG_ARGS_ENTER,
         SledEntry::FunctionKinds::CUSTOM_EVENT};
-    if (Kind >= sizeof(Kinds) / sizeof(Kinds[0]))
+    if (Kind >= std::size(Kinds))
       return errorCodeToError(
           std::make_error_code(std::errc::executable_format_error));
     Entry.Kind = Kinds[Kind];