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| author | Luke Geeson <luke.geeson@arm.com> | 2020-02-11 16:57:25 +0000 |
|---|---|---|
| committer | Luke Geeson <luke.geeson@arm.com> | 2020-02-18 14:56:16 +0000 |
| commit | 4518aab289a090a668af0ca4ecde976e18fb2b1e (patch) | |
| tree | 69b7b20fcf9f04edcb5e3a56ae134b80af1df8e1 /llvm/lib | |
| parent | cd2c5af6dfd6e32ee7043894bcb42981ce99e8ac (diff) | |
| download | llvm-4518aab289a090a668af0ca4ecde976e18fb2b1e.zip llvm-4518aab289a090a668af0ca4ecde976e18fb2b1e.tar.gz llvm-4518aab289a090a668af0ca4ecde976e18fb2b1e.tar.bz2 | |
[AArch64] Add Cortex-A34 Support for clang and llvm
This patch upstreams support for the AArch64 Armv8-A cpu Cortex-A34.
In detail adding support for:
- mcpu option in clang
- AArch64 Target Features in clang
- llvm AArch64 TargetParser definitions
details of the cpu can be found here:
https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34
Reviewers: SjoerdMeijer
Reviewed By: SjoerdMeijer
Subscribers: SjoerdMeijer, kristof.beyls, hiraditya, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74483
Change-Id: Ida101fc544ca183a0a0e61a1277c8957855fde0b
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Support/Host.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64.td | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index 955c1b3..1597e6f7 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -178,6 +178,8 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The // values correspond to the "Part number" in the CP15/c0 register. The // contents are specified in the various processor manuals. + // This corresponds to the Main ID Register in Technical Reference Manuals. + // and is used in programs like sys-utils return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) .Case("0x926", "arm926ej-s") .Case("0xb02", "mpcore") @@ -190,6 +192,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { .Case("0xc20", "cortex-m0") .Case("0xc23", "cortex-m3") .Case("0xc24", "cortex-m4") + .Case("0xd02", "cortex-a34") .Case("0xd04", "cortex-a35") .Case("0xd03", "cortex-a53") .Case("0xd07", "cortex-a57") diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 6e0d949e..2e24e80 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -853,6 +853,7 @@ def : ProcessorModel<"generic", NoSchedModel, [ ]>; def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; +def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>; def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>; def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; |