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author | Felipe de Azevedo Piovezan <fpiovezan@apple.com> | 2023-05-01 08:18:24 -0400 |
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committer | Felipe de Azevedo Piovezan <fpiovezan@apple.com> | 2023-05-12 11:55:39 -0400 |
commit | 3f6e4e5b6e9451adf0fc21f3c45076d987fbbfd2 (patch) | |
tree | 9e5028f8721e8ec94e5c48fffc3630692fda8028 /llvm/lib | |
parent | 42bd81410e3650354cc4d725e1d51238e0259771 (diff) | |
download | llvm-3f6e4e5b6e9451adf0fc21f3c45076d987fbbfd2.zip llvm-3f6e4e5b6e9451adf0fc21f3c45076d987fbbfd2.tar.gz llvm-3f6e4e5b6e9451adf0fc21f3c45076d987fbbfd2.tar.bz2 |
[IRTranslator][DebugInfo] Implement translation of entry_value vars
This commit implements IRTranslator lowering of dbg.declare intrinsics targeting
swiftasync Arguments, by putting them in the MachineFunction's table of
variables whose location doesn't change throughout the function.
Depends on D149881
Differential Revision: https://reviews.llvm.org/D149882
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 45 |
1 files changed, 40 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 94fd394d..5efb7ee 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1879,6 +1879,37 @@ bool IRTranslator::translateConstrainedFPIntrinsic( return true; } +std::optional<MCRegister> IRTranslator::getArgPhysReg(Argument &Arg) { + auto VRegs = getOrCreateVRegs(Arg); + if (VRegs.size() != 1) + return std::nullopt; + + // Arguments are lowered as a copy of a livein physical register. + auto *VRegDef = MF->getRegInfo().getVRegDef(VRegs[0]); + if (!VRegDef || !VRegDef->isCopy()) + return std::nullopt; + return VRegDef->getOperand(1).getReg().asMCReg(); +} + +bool IRTranslator::translateIfEntryValueArgument( + const DbgDeclareInst &DebugInst) { + auto *Arg = dyn_cast<Argument>(DebugInst.getAddress()); + if (!Arg) + return false; + + const DIExpression *Expr = DebugInst.getExpression(); + if (!Expr->isEntryValue()) + return false; + + std::optional<MCRegister> PhysReg = getArgPhysReg(*Arg); + if (!PhysReg) + return false; + + MF->setVariableDbgInfo(DebugInst.getVariable(), Expr, *PhysReg, + DebugInst.getDebugLoc()); + return true; +} + bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, MachineIRBuilder &MIRBuilder) { if (auto *MI = dyn_cast<AnyMemIntrinsic>(&CI)) { @@ -1945,12 +1976,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, // instructions (in fact, they get ignored if they *do* exist). MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(), getOrCreateFrameIndex(*AI), DI.getDebugLoc()); - } else { - // A dbg.declare describes the address of a source variable, so lower it - // into an indirect DBG_VALUE. - MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), - DI.getVariable(), DI.getExpression()); + return true; } + + if (translateIfEntryValueArgument(DI)) + return true; + + // A dbg.declare describes the address of a source variable, so lower it + // into an indirect DBG_VALUE. + MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address), + DI.getVariable(), DI.getExpression()); return true; } case Intrinsic::dbg_label: { |