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authorKazu Hirata <kazu@google.com>2025-03-08 01:02:22 -0800
committerGitHub <noreply@github.com>2025-03-08 01:02:22 -0800
commit3e0c503e3e259ce63b08e5d780a82fe7385dfbc8 (patch)
tree624e122942f77f9d12361c5f9f9d004b420b4ebe /llvm/lib
parenteef0ddaeb8e13d975ffbc97b1733a0cf19e0b572 (diff)
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[SPIRV] Avoid repeated hash lookups (NFC) (#130391)
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp7
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index baacd58..3779a4b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -120,8 +120,9 @@ addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR,
}
for (MachineInstr *MI : ToErase) {
Register Reg = MI->getOperand(2).getReg();
- if (RegsAlreadyAddedToDT.contains(MI))
- Reg = RegsAlreadyAddedToDT[MI];
+ auto It = RegsAlreadyAddedToDT.find(MI);
+ if (It != RegsAlreadyAddedToDT.end())
+ Reg = It->second;
auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg());
if (!MRI.getRegClassOrNull(Reg) && RC)
MRI.setRegClass(Reg, RC);
@@ -652,7 +653,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
}
for (MachineInstr *MI : ToErase) {
auto It = RegsAlreadyAddedToDT.find(MI);
- if (RegsAlreadyAddedToDT.contains(MI))
+ if (It != RegsAlreadyAddedToDT.end())
MRI.replaceRegWith(MI->getOperand(0).getReg(), It->second);
MI->eraseFromParent();
}