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| author | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2023-02-07 10:45:29 +0000 |
|---|---|---|
| committer | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2023-02-07 11:10:17 +0000 |
| commit | 385992105ef72765582c8f8547b554878d5776e9 (patch) | |
| tree | 448edbf08942446932354757ccfee86f527d7adb /llvm/lib | |
| parent | 8e3d7cf5dee8d80dce1004a66c8a375b9d3b5dca (diff) | |
| download | llvm-385992105ef72765582c8f8547b554878d5776e9.zip llvm-385992105ef72765582c8f8547b554878d5776e9.tar.gz llvm-385992105ef72765582c8f8547b554878d5776e9.tar.bz2 | |
[AArch64][SME2] Add multi-vector floating point min/max number intrinsics
Adds IR intrinsics for the following SME2 instructions:
- fmaxnm/fminnm (single, 2 & 4 vector)
- fmaxnm/fminnm (multi, 2 & 4 vector)
NOTE: These intrinsics are still in development and are subject to future changes.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D142732
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 93df312..a9ee346 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -5200,6 +5200,62 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { AArch64::FMIN_VG4_4Z4Z_D})) SelectDestructiveMultiIntrinsic(Node, 4, true, Op); return; + case Intrinsic::aarch64_sve_fmaxnm_single_x2 : + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMAXNM_VG2_2ZZ_H, AArch64::FMAXNM_VG2_2ZZ_S, + AArch64::FMAXNM_VG2_2ZZ_D})) + SelectDestructiveMultiIntrinsic(Node, 2, false, Op); + return; + case Intrinsic::aarch64_sve_fmaxnm_single_x4 : + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMAXNM_VG4_4ZZ_H, AArch64::FMAXNM_VG4_4ZZ_S, + AArch64::FMAXNM_VG4_4ZZ_D})) + SelectDestructiveMultiIntrinsic(Node, 4, false, Op); + return; + case Intrinsic::aarch64_sve_fminnm_single_x2: + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMINNM_VG2_2ZZ_H, AArch64::FMINNM_VG2_2ZZ_S, + AArch64::FMINNM_VG2_2ZZ_D})) + SelectDestructiveMultiIntrinsic(Node, 2, false, Op); + return; + case Intrinsic::aarch64_sve_fminnm_single_x4: + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMINNM_VG4_4ZZ_H, AArch64::FMINNM_VG4_4ZZ_S, + AArch64::FMINNM_VG4_4ZZ_D})) + SelectDestructiveMultiIntrinsic(Node, 4, false, Op); + return; + case Intrinsic::aarch64_sve_fmaxnm_x2: + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMAXNM_VG2_2Z2Z_H, AArch64::FMAXNM_VG2_2Z2Z_S, + AArch64::FMAXNM_VG2_2Z2Z_D})) + SelectDestructiveMultiIntrinsic(Node, 2, true, Op); + return; + case Intrinsic::aarch64_sve_fmaxnm_x4: + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMAXNM_VG4_4Z4Z_H, AArch64::FMAXNM_VG4_4Z4Z_S, + AArch64::FMAXNM_VG4_4Z4Z_D})) + SelectDestructiveMultiIntrinsic(Node, 4, true, Op); + return; + case Intrinsic::aarch64_sve_fminnm_x2: + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMINNM_VG2_2Z2Z_H, AArch64::FMINNM_VG2_2Z2Z_S, + AArch64::FMINNM_VG2_2Z2Z_D})) + SelectDestructiveMultiIntrinsic(Node, 2, true, Op); + return; + case Intrinsic::aarch64_sve_fminnm_x4: + if (auto Op = SelectOpcodeFromVT<SelectTypeKind::FP>( + Node->getValueType(0), + {0, AArch64::FMINNM_VG4_4Z4Z_H, AArch64::FMINNM_VG4_4Z4Z_S, + AArch64::FMINNM_VG4_4Z4Z_D})) + SelectDestructiveMultiIntrinsic(Node, 4, true, Op); + return; case Intrinsic::aarch64_sve_fcvts_x2: SelectCVTIntrinsic(Node, 2, AArch64::FCVTZS_2Z2Z_StoS); return; |