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author | Sander de Smalen <sander.desmalen@arm.com> | 2022-07-15 13:53:42 +0100 |
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committer | Sander de Smalen <sander.desmalen@arm.com> | 2022-07-26 15:07:41 +0100 |
commit | 370ff43a15c90eca61dfa5715c7da82f1a4709f8 (patch) | |
tree | a052137fadec749d397ac473a483dfcffe4eabec /llvm/lib | |
parent | 5a594c28315d8b458e626aa2d88de7c1e1b96689 (diff) | |
download | llvm-370ff43a15c90eca61dfa5715c7da82f1a4709f8.zip llvm-370ff43a15c90eca61dfa5715c7da82f1a4709f8.tar.gz llvm-370ff43a15c90eca61dfa5715c7da82f1a4709f8.tar.bz2 |
[AArch64][SVE] Consider more intrinsics in 'isZeroingInactiveLanes'.
This fixes some PTEST regressions introduced by D129282.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D129851
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index bc57afd..7df43c3 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -255,6 +255,12 @@ static bool isZeroingInactiveLanes(SDValue Op) { return false; case Intrinsic::aarch64_sve_ptrue: case Intrinsic::aarch64_sve_pnext: + case Intrinsic::aarch64_sve_cmpeq: + case Intrinsic::aarch64_sve_cmpne: + case Intrinsic::aarch64_sve_cmpge: + case Intrinsic::aarch64_sve_cmpgt: + case Intrinsic::aarch64_sve_cmphs: + case Intrinsic::aarch64_sve_cmphi: case Intrinsic::aarch64_sve_cmpeq_wide: case Intrinsic::aarch64_sve_cmpne_wide: case Intrinsic::aarch64_sve_cmpge_wide: @@ -265,6 +271,11 @@ static bool isZeroingInactiveLanes(SDValue Op) { case Intrinsic::aarch64_sve_cmphi_wide: case Intrinsic::aarch64_sve_cmplo_wide: case Intrinsic::aarch64_sve_cmpls_wide: + case Intrinsic::aarch64_sve_fcmpeq: + case Intrinsic::aarch64_sve_fcmpne: + case Intrinsic::aarch64_sve_fcmpge: + case Intrinsic::aarch64_sve_fcmpgt: + case Intrinsic::aarch64_sve_fcmpuo: return true; } } |