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authorCraig Topper <craig.topper@sifive.com>2025-03-29 09:56:46 -0700
committerCraig Topper <craig.topper@sifive.com>2025-03-29 11:14:06 -0700
commit2ec88374e07f8ec395b7bf414bf1bdda88cebfc6 (patch)
treeb476a91c3252dba3cb4a5824cb64bb5102414fbf /llvm/lib
parentb9b39db5d7677710f1d00dc8ff5844ad2abb269f (diff)
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[X86] Use MCRegister. NFC
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/AsmParser/X86Operand.h4
-rw-r--r--llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp4
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.cpp2
-rw-r--r--llvm/lib/Target/X86/X86MCInstLower.cpp2
4 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86Operand.h b/llvm/lib/Target/X86/AsmParser/X86Operand.h
index 1fa82a16..c143ebd 100644
--- a/llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ b/llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -628,8 +628,8 @@ struct X86Operand final : public MCParsedAsmOperand {
void addTILEPairOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- unsigned Reg = getReg();
- switch (Reg) {
+ MCRegister Reg = getReg();
+ switch (Reg.id()) {
default:
llvm_unreachable("Invalid tile register!");
case X86::TMM0:
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index b5b36e7..3653f5a 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -1181,8 +1181,8 @@ class DarwinX86AsmBackend : public X86AsmBackend {
unsigned StackDivide; ///< Amount to adjust stack size by.
protected:
/// Size of a "push" instruction for the given register.
- unsigned PushInstrSize(unsigned Reg) const {
- switch (Reg) {
+ unsigned PushInstrSize(MCRegister Reg) const {
+ switch (Reg.id()) {
case X86::EBX:
case X86::ECX:
case X86::EDX:
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index d879d99..78be02d 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -6239,7 +6239,7 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
}
if (MI.getOpcode() == X86::AVX512_256_SET0) {
// No VLX so we must reference a zmm.
- unsigned ZReg =
+ MCRegister ZReg =
TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
MIB->getOperand(0).setReg(ZReg);
}
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 3f6cd55..52332c4 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -444,7 +444,7 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
}
OutMI.setOpcode(NewOpc);
// Duplicate the destination.
- unsigned DestReg = OutMI.getOperand(0).getReg();
+ MCRegister DestReg = OutMI.getOperand(0).getReg();
OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg));
break;
}