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authorBrandon Wu <brandon.wu@sifive.com>2024-11-17 18:52:49 +0800
committerGitHub <noreply@github.com>2024-11-17 18:52:49 +0800
commit206ee7191834186ae78bf57fcf21d29dd7ce24cf (patch)
tree1cd64147445e2b74e81d951e0982c0f778e7acaa /llvm/lib
parent811186764d1add4d83972db3ad0d2e7c96bb15a7 (diff)
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[RISCV] Change vector tuple type's TypeSize to scalable (#114329)
Vector tuple is basically multiple grouped vector, so its size is also determined by vscale, we need not to model it as a vector type but its size need to be scalable.
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/ValueTypes.cpp2
-rw-r--r--llvm/lib/Target/RISCV/RISCVISelLowering.cpp46
2 files changed, 27 insertions, 21 deletions
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index e3c746b..2c80eee 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -163,7 +163,7 @@ std::string EVT::getEVTString() const {
switch (V.SimpleTy) {
default:
if (isRISCVVectorTuple()) {
- unsigned Sz = getSizeInBits();
+ unsigned Sz = getSizeInBits().getKnownMinValue();
unsigned NF = getRISCVVectorTupleNumFields();
unsigned MinNumElts = Sz / (NF * 8);
return "riscv_nxv" + utostr(MinNumElts) + "i8x" + utostr(NF);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 267a349..5f970ff 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2411,8 +2411,9 @@ unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) {
unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {
if (VT.isRISCVVectorTuple()) {
unsigned NF = VT.getRISCVVectorTupleNumFields();
- unsigned RegsPerField = std::max(1U, (unsigned)VT.getSizeInBits() /
- (NF * RISCV::RVVBitsPerBlock));
+ unsigned RegsPerField =
+ std::max(1U, (unsigned)VT.getSizeInBits().getKnownMinValue() /
+ (NF * RISCV::RVVBitsPerBlock));
switch (RegsPerField) {
case 1:
if (NF == 2)
@@ -7036,7 +7037,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT();
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
- unsigned Sz = VecTy.getSizeInBits();
+ unsigned Sz = VecTy.getSizeInBits().getKnownMinValue();
unsigned NumElts = Sz / (NF * 8);
int Log2LMUL = Log2_64(NumElts) - 3;
@@ -7079,7 +7080,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT();
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
- unsigned Sz = VecTy.getSizeInBits();
+ unsigned Sz = VecTy.getSizeInBits().getKnownMinValue();
unsigned NumElts = Sz / (NF * 8);
int Log2LMUL = Log2_64(NumElts) - 3;
@@ -21372,6 +21373,27 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
return true;
}
+ if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
+#ifndef NDEBUG
+ unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
+ [[maybe_unused]] unsigned ValLMUL =
+ divideCeil(ValueVT.getSizeInBits().getKnownMinValue(),
+ ValNF * RISCV::RVVBitsPerBlock);
+ unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
+ [[maybe_unused]] unsigned PartLMUL =
+ divideCeil(PartVT.getSizeInBits().getKnownMinValue(),
+ PartNF * RISCV::RVVBitsPerBlock);
+ assert(ValNF == PartNF && ValLMUL == PartLMUL &&
+ "RISC-V vector tuple type only accepts same register class type "
+ "TUPLE_INSERT");
+#endif
+
+ Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
+ Val, DAG.getVectorIdxConstant(0, DL));
+ Parts[0] = Val;
+ return true;
+ }
+
if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
LLVMContext &Context = *DAG.getContext();
EVT ValueEltVT = ValueVT.getVectorElementType();
@@ -21407,22 +21429,6 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
}
}
- if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
- unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
- [[maybe_unused]] unsigned ValLMUL =
- divideCeil(ValueVT.getSizeInBits(), ValNF * RISCV::RVVBitsPerBlock);
- unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
- [[maybe_unused]] unsigned PartLMUL =
- divideCeil(PartVT.getSizeInBits(), PartNF * RISCV::RVVBitsPerBlock);
- assert(ValNF == PartNF && ValLMUL == PartLMUL &&
- "RISC-V vector tuple type only accepts same register class type "
- "TUPLE_INSERT");
-
- Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
- Val, DAG.getVectorIdxConstant(0, DL));
- Parts[0] = Val;
- return true;
- }
return false;
}