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authorCraig Topper <craig.topper@intel.com>2018-11-16 01:16:51 +0000
committerCraig Topper <craig.topper@intel.com>2018-11-16 01:16:51 +0000
commit1acafd863f53810c21cf73603f767314992aa27b (patch)
tree06a1fe3393c807be7fb70449ad2600045ff9b103 /llvm/lib
parent7610033f56a9e7b04138774334590f0bdd3f79db (diff)
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[X86] Update a couple comments to remove a mention of a sign extending that no longer happens. NFC
llvm-svn: 347010
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2ba2934..b496a1f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -23367,7 +23367,7 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget,
"Pre-AVX2 support only supports v16i8 multiplication");
MVT ExVT = MVT::v8i16;
- // Extract the lo parts and sign extend to i16
+ // Extract the lo parts to any extend to i16
// We're going to mask off the low byte of each result element of the
// pmullw, so it doesn't matter what's in the high byte of each 16-bit
// element.
@@ -23378,11 +23378,11 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget,
ALo = DAG.getBitcast(ExVT, ALo);
BLo = DAG.getBitcast(ExVT, BLo);
- // Extract the hi parts and sign extend to i16
+ // Extract the hi parts to any extend to i16
// We're going to mask off the low byte of each result element of the
// pmullw, so it doesn't matter what's in the high byte of each 16-bit
// element.
- const int HiShufMask[] = {8, -1, 9, -1, 10, -1, 11, -1,
+ const int HiShufMask[] = { 8, -1, 9, -1, 10, -1, 11, -1,
12, -1, 13, -1, 14, -1, 15, -1};
SDValue AHi = DAG.getVectorShuffle(VT, dl, A, A, HiShufMask);
SDValue BHi = DAG.getVectorShuffle(VT, dl, B, B, HiShufMask);