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| author | CarolineConcatto <caroline.concatto@arm.com> | 2024-05-01 08:39:59 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-01 08:39:59 +0100 |
| commit | 14b66fe5f36aaad627baa7f624a4997a7956d51a (patch) | |
| tree | 209cf61b3399be21a031e367982aaf7e268e6347 /llvm/lib | |
| parent | 23f0f7bda0c16fa4a2ddb4ef60d5d146dbfac572 (diff) | |
| download | llvm-14b66fe5f36aaad627baa7f624a4997a7956d51a.zip llvm-14b66fe5f36aaad627baa7f624a4997a7956d51a.tar.gz llvm-14b66fe5f36aaad627baa7f624a4997a7956d51a.tar.bz2 | |
[AArch64][MC]Add diagnostic message for Multiple of 2/4 for ZPR128 (#90600)
This patch fix the crash reported in:
https://github.com/llvm/llvm-project/issues/90589
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index a3b966a..c9bba9b 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -6136,6 +6136,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, case Match_InvalidSVEVectorListMul2x16: case Match_InvalidSVEVectorListMul2x32: case Match_InvalidSVEVectorListMul2x64: + case Match_InvalidSVEVectorListMul2x128: return Error(Loc, "Invalid vector list, expected list with 2 consecutive " "SVE vectors, where the first vector is a multiple of 2 " "and with matching element types"); @@ -6143,6 +6144,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, case Match_InvalidSVEVectorListMul4x16: case Match_InvalidSVEVectorListMul4x32: case Match_InvalidSVEVectorListMul4x64: + case Match_InvalidSVEVectorListMul4x128: return Error(Loc, "Invalid vector list, expected list with 4 consecutive " "SVE vectors, where the first vector is a multiple of 4 " "and with matching element types"); @@ -6739,10 +6741,12 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidSVEVectorListMul2x16: case Match_InvalidSVEVectorListMul2x32: case Match_InvalidSVEVectorListMul2x64: + case Match_InvalidSVEVectorListMul2x128: case Match_InvalidSVEVectorListMul4x8: case Match_InvalidSVEVectorListMul4x16: case Match_InvalidSVEVectorListMul4x32: case Match_InvalidSVEVectorListMul4x64: + case Match_InvalidSVEVectorListMul4x128: case Match_InvalidSVEVectorListStrided2x8: case Match_InvalidSVEVectorListStrided2x16: case Match_InvalidSVEVectorListStrided2x32: |