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authorJames Molloy <james.molloy@arm.com>2014-06-12 15:18:33 +0000
committerJames Molloy <james.molloy@arm.com>2014-06-12 15:18:33 +0000
commit1417b0be3e8fce748a71fd827a2a6a5ce3d9d145 (patch)
treecf3c2eb23b4da9e65920f35d5933fc52b2b3e2a1 /llvm/lib
parent3d3ea53f32c0638ccd643af3e67807e0a8b325ab (diff)
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Disable the load/store optimization pass for Thumb-1.
Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out. Patch by Moritz Roth! llvm-svn: 210789
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.cpp10
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 6ef2ea4..c1e866b 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -265,7 +265,8 @@ bool ARMPassConfig::addInstSelector() {
}
bool ARMPassConfig::addPreRegAlloc() {
- if (getOptLevel() != CodeGenOpt::None)
+ // FIXME: Temporarily disabling Thumb-1 pre-RA Load/Store optimization pass
+ if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
addPass(createARMLoadStoreOptimizationPass(true));
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
addPass(createMLxExpansionPass());
@@ -280,8 +281,11 @@ bool ARMPassConfig::addPreRegAlloc() {
bool ARMPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None) {
- addPass(createARMLoadStoreOptimizationPass());
- printAndVerify("After ARM load / store optimizer");
+ // FIXME: Temporarily disabling Thumb-1 post-RA Load/Store optimization pass
+ if (!getARMSubtarget().isThumb1Only()) {
+ addPass(createARMLoadStoreOptimizationPass());
+ printAndVerify("After ARM load / store optimizer");
+ }
if (getARMSubtarget().hasNEON())
addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));