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authorDavid Green <david.green@arm.com>2019-08-15 10:41:42 +0000
committerDavid Green <david.green@arm.com>2019-08-15 10:41:42 +0000
commit0ff2296a49aacdb6c3896e7a2334328dcbf55c0d (patch)
tree8439e968296206a3af599691930325f6d8ed836e /llvm/lib
parent643adb55769ecb12e0377dab60de50def15d2cea (diff)
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[ARM] MVE predicate store patterns
Stack loads and stores were already working, but direct stores were not. This adds the patterns for them, same as predicate loads. Differential Revision: https://reviews.llvm.org/D66213 llvm-svn: 368988
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrMVE.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index b4a7a13..cd67081 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -4928,6 +4928,13 @@ let Predicates = [HasMVEInt] in {
(v8i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
def : Pat<(v4i1 (load t2addrmode_imm7<2>:$addr)),
(v4i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
+
+ def : Pat<(store (v4i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
+ (VSTR_P0_off VCCR:$val, t2addrmode_imm7<2>:$addr)>;
+ def : Pat<(store (v8i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
+ (VSTR_P0_off VCCR:$val, t2addrmode_imm7<2>:$addr)>;
+ def : Pat<(store (v16i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
+ (VSTR_P0_off VCCR:$val, t2addrmode_imm7<2>:$addr)>;
}