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| author | Phoebe Wang <phoebe.wang@intel.com> | 2024-03-04 18:09:41 +0800 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2024-03-19 14:06:42 -0700 |
| commit | 26a1d6601d727a96f4301d0d8647b5a42760ae0c (patch) | |
| tree | 232815b14ea830e8ab92f111fdb4844e7e5a3f76 /llvm/lib | |
| parent | 0bf7ff1028fb7cc81324e9c38c585e6533b754e4 (diff) | |
| download | llvm-llvmorg-18.1.2.zip llvm-llvmorg-18.1.2.tar.gz llvm-llvmorg-18.1.2.tar.bz2 | |
[X86] Add missing subvector_subreg_lowering for BF16 (#83720)llvmorg-18.1.2
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrVecCompiler.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td b/llvm/lib/Target/X86/X86InstrVecCompiler.td index bbd19cf..461b2ba 100644 --- a/llvm/lib/Target/X86/X86InstrVecCompiler.td +++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td @@ -83,6 +83,7 @@ defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>; defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>; defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>; defm : subvector_subreg_lowering<VR128, v8f16, VR256, v16f16, sub_xmm>; +defm : subvector_subreg_lowering<VR128, v8bf16, VR256, v16bf16, sub_xmm>; // A 128-bit subvector extract from the first 512-bit vector position is a // subregister copy that needs no instruction. Likewise, a 128-bit subvector @@ -95,6 +96,7 @@ defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>; defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>; defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>; defm : subvector_subreg_lowering<VR128, v8f16, VR512, v32f16, sub_xmm>; +defm : subvector_subreg_lowering<VR128, v8bf16, VR512, v32bf16, sub_xmm>; // A 128-bit subvector extract from the first 512-bit vector position is a // subregister copy that needs no instruction. Likewise, a 128-bit subvector @@ -107,6 +109,7 @@ defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>; defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>; defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>; defm : subvector_subreg_lowering<VR256, v16f16, VR512, v32f16, sub_ymm>; +defm : subvector_subreg_lowering<VR256, v16bf16, VR512, v32bf16, sub_ymm>; // If we're inserting into an all zeros vector, just use a plain move which |