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author | paperchalice <liujunchang97@outlook.com> | 2024-06-02 09:12:33 +0800 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-06-02 09:12:33 +0800 |
commit | d2cdc8ab45d74f8691f73cb5a2b8c431585cd449 (patch) | |
tree | 0aa5cbc5236038b0496289d33c037714bf767c32 /llvm/lib/Target | |
parent | 0310f7f2d0c56a5697710251cec9803cbf7b4d56 (diff) | |
download | llvm-d2cdc8ab45d74f8691f73cb5a2b8c431585cd449.zip llvm-d2cdc8ab45d74f8691f73cb5a2b8c431585cd449.tar.gz llvm-d2cdc8ab45d74f8691f73cb5a2b8c431585cd449.tar.bz2 |
[NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)
Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.
Diffstat (limited to 'llvm/lib/Target')
85 files changed, 496 insertions, 215 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h index b70fbe4..0f0a22e 100644 --- a/llvm/lib/Target/AArch64/AArch64.h +++ b/llvm/lib/Target/AArch64/AArch64.h @@ -85,7 +85,7 @@ void initializeAArch64CompressJumpTablesPass(PassRegistry&); void initializeAArch64CondBrTuningPass(PassRegistry &); void initializeAArch64ConditionOptimizerPass(PassRegistry&); void initializeAArch64ConditionalComparesPass(PassRegistry &); -void initializeAArch64DAGToDAGISelPass(PassRegistry &); +void initializeAArch64DAGToDAGISelLegacyPass(PassRegistry &); void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&); void initializeAArch64ExpandPseudoPass(PassRegistry &); void initializeAArch64GlobalsTaggingPass(PassRegistry &); diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 8fd58f4..248778f 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -44,13 +44,11 @@ class AArch64DAGToDAGISel : public SelectionDAGISel { const AArch64Subtarget *Subtarget; public: - static char ID; - AArch64DAGToDAGISel() = delete; explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<AArch64Subtarget>(); @@ -507,11 +505,20 @@ private: bool SelectAllActivePredicate(SDValue N); bool SelectAnyPredicate(SDValue N); }; + +class AArch64DAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit AArch64DAGToDAGISelLegacy(AArch64TargetMachine &tm, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<AArch64DAGToDAGISel>(tm, OptLevel)) {} +}; } // end anonymous namespace -char AArch64DAGToDAGISel::ID = 0; +char AArch64DAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(AArch64DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(AArch64DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) /// isIntImmediate - This method tests to see if the node is a constant /// operand. If so Imm will receive the 32-bit value. @@ -6867,7 +6874,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { /// AArch64-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new AArch64DAGToDAGISel(TM, OptLevel); + return new AArch64DAGToDAGISelLegacy(TM, OptLevel); } /// When \p PredVT is a scalable vector predicate in the form diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 945ab5c..30f0ceaf 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -258,7 +258,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() { initializeAArch64StackTaggingPass(*PR); initializeAArch64StackTaggingPreRAPass(*PR); initializeAArch64LowerHomogeneousPrologEpilogPass(*PR); - initializeAArch64DAGToDAGISelPass(*PR); + initializeAArch64DAGToDAGISelLegacyPass(*PR); initializeAArch64GlobalsTaggingPass(*PR); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 6016bd5..46cc5f3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -81,7 +81,7 @@ struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> { PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); }; -void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); +void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &); void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); extern char &AMDGPUMachineCFGStructurizerID; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp index 01ab61a..7c353fd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp @@ -7,7 +7,9 @@ //===----------------------------------------------------------------------===// #include "AMDGPUCodeGenPassBuilder.h" +#include "AMDGPUISelDAGToDAG.h" #include "AMDGPUTargetMachine.h" +#include "llvm/Analysis/UniformityAnalysis.h" using namespace llvm; @@ -25,6 +27,8 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder( void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const { // TODO: Add passes pre instruction selection. + // Test only, convert to real IR passes in future. + addPass(RequireAnalysisPass<UniformityInfoAnalysis, Function>()); } void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass, @@ -32,7 +36,7 @@ void AMDGPUCodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass, // TODO: Add AsmPrinter. } -Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &) const { - // TODO: Add instruction selector. +Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const { + addPass(AMDGPUISelDAGToDAGPass(TM)); return Error::success(); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index e359573..3e2581d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -98,8 +98,9 @@ static SDValue stripExtractLoElt(SDValue In) { } // end anonymous namespace -INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "amdgpu-isel", - "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) +INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISelLegacy, "amdgpu-isel", + "AMDGPU DAG->DAG Pattern Instruction Selection", false, + false) INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo) INITIALIZE_PASS_DEPENDENCY(AMDGPUPerfHintAnalysis) INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass) @@ -107,19 +108,20 @@ INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) #endif -INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "amdgpu-isel", - "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) +INITIALIZE_PASS_END(AMDGPUDAGToDAGISelLegacy, "amdgpu-isel", + "AMDGPU DAG->DAG Pattern Instruction Selection", false, + false) /// This pass converts a legalized DAG into a AMDGPU-specific // DAG, ready for instruction scheduling. FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new AMDGPUDAGToDAGISel(TM, OptLevel); + return new AMDGPUDAGToDAGISelLegacy(TM, OptLevel); } AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) { + : SelectionDAGISel(TM, OptLevel) { EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG; } @@ -200,14 +202,14 @@ bool AMDGPUDAGToDAGISel::fp16SrcZerosHighBits(unsigned Opc) const { } } -void AMDGPUDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { +void AMDGPUDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<AMDGPUArgumentUsageInfo>(); AU.addRequired<UniformityInfoWrapperPass>(); #ifdef EXPENSIVE_CHECKS AU.addRequired<DominatorTreeWrapperPass>(); AU.addRequired<LoopInfoWrapperPass>(); #endif - SelectionDAGISel::getAnalysisUsage(AU); + SelectionDAGISelLegacy::getAnalysisUsage(AU); } bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const { @@ -771,10 +773,14 @@ bool AMDGPUDAGToDAGISel::isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS, return false; } -StringRef AMDGPUDAGToDAGISel::getPassName() const { +StringRef AMDGPUDAGToDAGISelLegacy::getPassName() const { return "AMDGPU DAG->DAG Pattern Instruction Selection"; } +AMDGPUISelDAGToDAGPass::AMDGPUISelDAGToDAGPass(TargetMachine &TM) + : SelectionDAGISelPass( + std::make_unique<AMDGPUDAGToDAGISel>(TM, TM.getOptLevel())) {} + //===----------------------------------------------------------------------===// // Complex Patterns //===----------------------------------------------------------------------===// @@ -3607,4 +3613,9 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() { } while (IsModified); } -char AMDGPUDAGToDAGISel::ID = 0; +AMDGPUDAGToDAGISelLegacy::AMDGPUDAGToDAGISelLegacy(TargetMachine &TM, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<AMDGPUDAGToDAGISel>(TM, OptLevel)) {} + +char AMDGPUDAGToDAGISelLegacy::ID = 0; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h index 53d25b4..b5b374b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h @@ -83,21 +83,14 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel { bool fp16SrcZerosHighBits(unsigned Opc) const; public: - static char ID; - AMDGPUDAGToDAGISel() = delete; explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOptLevel OptLevel); - ~AMDGPUDAGToDAGISel() override = default; - - void getAnalysisUsage(AnalysisUsage &AU) const override; - - bool matchLoadD16FromBuildVector(SDNode *N) const; bool runOnMachineFunction(MachineFunction &MF) override; + bool matchLoadD16FromBuildVector(SDNode *N) const; void PreprocessISelDAG() override; void Select(SDNode *N) override; - StringRef getPassName() const override; void PostprocessISelDAG() override; protected: @@ -288,4 +281,19 @@ protected: #include "AMDGPUGenDAGISel.inc" }; +class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass { +public: + AMDGPUISelDAGToDAGPass(TargetMachine &TM); +}; + +class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + + AMDGPUDAGToDAGISelLegacy(TargetMachine &TM, CodeGenOptLevel OptLevel); + + void getAnalysisUsage(AnalysisUsage &AU) const override; + StringRef getPassName() const override; +}; + #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index 90f36fa..57fc331 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -71,3 +71,9 @@ FUNCTION_PASS_WITH_PARAMS( }, parseAMDGPUAtomicOptimizerStrategy, "strategy=dpp|iterative|none") #undef FUNCTION_PASS_WITH_PARAMS + +#ifndef MACHINE_FUNCTION_PASS +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) +#endif +MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this)) +#undef MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index dbbfe34..9c94ca1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -19,6 +19,7 @@ #include "AMDGPUCtorDtorLowering.h" #include "AMDGPUExportClustering.h" #include "AMDGPUIGroupLP.h" +#include "AMDGPUISelDAGToDAG.h" #include "AMDGPUMacroFusion.h" #include "AMDGPURegBankSelect.h" #include "AMDGPUSplitModule.h" @@ -387,7 +388,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeR600ExpandSpecialInstrsPassPass(*PR); initializeR600VectorRegMergerPass(*PR); initializeGlobalISel(*PR); - initializeAMDGPUDAGToDAGISelPass(*PR); + initializeAMDGPUDAGToDAGISelLegacyPass(*PR); initializeGCNDPPCombinePass(*PR); initializeSILowerI1CopiesPass(*PR); initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR); diff --git a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp index 293db13..28bcf72 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp @@ -48,6 +48,17 @@ protected: // Include the pieces autogenerated from the target description. #include "R600GenDAGISel.inc" }; + +class R600DAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit R600DAGToDAGISelLegacy(TargetMachine &TM, CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<R600DAGToDAGISel>(TM, OptLevel)) {} +}; + +char R600DAGToDAGISelLegacy::ID = 0; + } // namespace bool R600DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { @@ -184,5 +195,5 @@ bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base, // DAG, ready for instruction scheduling. FunctionPass *llvm::createR600ISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new R600DAGToDAGISel(TM, OptLevel); + return new R600DAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 7cde09c..4d8667a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3087,9 +3087,12 @@ SDValue SITargetLowering::LowerFormalArguments( if (IsEntryFunc) allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics); - auto &ArgUsageInfo = - DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); - ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo()); + // DAG.getPass() returns nullptr when using new pass manager. + // TODO: Use DAG.getMFAM() to access analysis result. + if (DAG.getPass()) { + auto &ArgUsageInfo = DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); + ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo()); + } unsigned StackArgSize = CCInfo.getStackSize(); Info->setBytesInStackArgArea(StackArgSize); @@ -3301,9 +3304,13 @@ void SITargetLowering::passSpecialInputs( const AMDGPUFunctionArgInfo *CalleeArgInfo = &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo; if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) { - auto &ArgUsageInfo = - DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); - CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc); + // DAG.getPass() returns nullptr when using new pass manager. + // TODO: Use DAG.getMFAM() to access analysis result. + if (DAG.getPass()) { + auto &ArgUsageInfo = + DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>(); + CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc); + } } // TODO: Unify with private memory register handling. This is complicated by diff --git a/llvm/lib/Target/ARC/ARC.h b/llvm/lib/Target/ARC/ARC.h index b81016d..459f79c 100644 --- a/llvm/lib/Target/ARC/ARC.h +++ b/llvm/lib/Target/ARC/ARC.h @@ -27,7 +27,7 @@ FunctionPass *createARCISelDag(ARCTargetMachine &TM, CodeGenOptLevel OptLevel); FunctionPass *createARCExpandPseudosPass(); FunctionPass *createARCOptAddrMode(); FunctionPass *createARCBranchFinalizePass(); -void initializeARCDAGToDAGISelPass(PassRegistry &); +void initializeARCDAGToDAGISelLegacyPass(PassRegistry &); } // end namespace llvm diff --git a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp index 17c2d7b..5e6cfa5 100644 --- a/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp @@ -41,12 +41,10 @@ namespace { class ARCDAGToDAGISel : public SelectionDAGISel { public: - static char ID; - ARCDAGToDAGISel() = delete; ARCDAGToDAGISel(ARCTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) {} + : SelectionDAGISel(TM, OptLevel) {} void Select(SDNode *N) override; @@ -60,17 +58,25 @@ public: #include "ARCGenDAGISel.inc" }; -char ARCDAGToDAGISel::ID; +class ARCDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit ARCDAGToDAGISelLegacy(ARCTargetMachine &TM, CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<ARCDAGToDAGISel>(TM, OptLevel)) {} +}; + +char ARCDAGToDAGISelLegacy::ID; } // end anonymous namespace -INITIALIZE_PASS(ARCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(ARCDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) /// This pass converts a legalized DAG into a ARC-specific DAG, ready for /// instruction scheduling. FunctionPass *llvm::createARCISelDag(ARCTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new ARCDAGToDAGISel(TM, OptLevel); + return new ARCDAGToDAGISelLegacy(TM, OptLevel); } bool ARCDAGToDAGISel::SelectAddrModeImm(SDValue Addr, SDValue &Base, diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index f50c3c0..5f021cf 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -97,7 +97,7 @@ MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo( extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() { RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeARCDAGToDAGISelPass(PR); + initializeARCDAGToDAGISelLegacyPass(PR); } TargetTransformInfo diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h index b96e018..0b7045e 100644 --- a/llvm/lib/Target/ARM/ARM.h +++ b/llvm/lib/Target/ARM/ARM.h @@ -64,7 +64,7 @@ void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, void initializeARMBlockPlacementPass(PassRegistry &); void initializeARMBranchTargetsPass(PassRegistry &); void initializeARMConstantIslandsPass(PassRegistry &); -void initializeARMDAGToDAGISelPass(PassRegistry &); +void initializeARMDAGToDAGISelLegacyPass(PassRegistry &); void initializeARMExpandPseudoPass(PassRegistry &); void initializeARMFixCortexA57AES1742098Pass(PassRegistry &); void initializeARMLoadStoreOptPass(PassRegistry &); diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 20dd3e7..7ffc643 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -59,12 +59,10 @@ class ARMDAGToDAGISel : public SelectionDAGISel { const ARMSubtarget *Subtarget; public: - static char ID; - ARMDAGToDAGISel() = delete; explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, tm, OptLevel) {} + : SelectionDAGISel(tm, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. @@ -362,11 +360,19 @@ private: /// selected when N would have been selected. void replaceDAGValue(const SDValue &N, SDValue M); }; + +class ARMDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + ARMDAGToDAGISelLegacy(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<ARMDAGToDAGISel>(tm, OptLevel)) {} +}; } -char ARMDAGToDAGISel::ID = 0; +char ARMDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(ARMDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(ARMDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) /// isInt32Immediate - This method tests to see if the node is a 32-bit constant /// operand. If so Imm will receive the 32-bit value. @@ -5886,5 +5892,5 @@ bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand( /// FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new ARMDAGToDAGISel(TM, OptLevel); + return new ARMDAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 4ef00df..7553778 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -110,7 +110,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() { initializeARMSLSHardeningPass(Registry); initializeMVELaneInterleavingPass(Registry); initializeARMFixCortexA57AES1742098Pass(Registry); - initializeARMDAGToDAGISelPass(Registry); + initializeARMDAGToDAGISelLegacyPass(Registry); } static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { diff --git a/llvm/lib/Target/AVR/AVR.h b/llvm/lib/Target/AVR/AVR.h index 4b1336e..0e67bb4 100644 --- a/llvm/lib/Target/AVR/AVR.h +++ b/llvm/lib/Target/AVR/AVR.h @@ -31,7 +31,7 @@ FunctionPass *createAVRExpandPseudoPass(); FunctionPass *createAVRFrameAnalyzerPass(); FunctionPass *createAVRBranchSelectionPass(); -void initializeAVRDAGToDAGISelPass(PassRegistry &); +void initializeAVRDAGToDAGISelLegacyPass(PassRegistry &); void initializeAVRExpandPseudoPass(PassRegistry &); void initializeAVRShiftExpandPass(PassRegistry &); diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp index e67a1e2..d6712eb 100644 --- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp +++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp @@ -34,7 +34,7 @@ public: AVRDAGToDAGISel() = delete; AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -60,11 +60,19 @@ private: const AVRSubtarget *Subtarget; }; +class AVRDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + AVRDAGToDAGISelLegacy(AVRTargetMachine &TM, CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<AVRDAGToDAGISel>(TM, OptLevel)) {} +}; + } // namespace -char AVRDAGToDAGISel::ID = 0; +char AVRDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(AVRDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(AVRDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { Subtarget = &MF.getSubtarget<AVRSubtarget>(); @@ -586,5 +594,5 @@ bool AVRDAGToDAGISel::trySelect(SDNode *N) { FunctionPass *llvm::createAVRISelDag(AVRTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new AVRDAGToDAGISel(TM, OptLevel); + return new AVRDAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp index e0776a6..a8c967f 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -95,7 +95,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() { auto &PR = *PassRegistry::getPassRegistry(); initializeAVRExpandPseudoPass(PR); initializeAVRShiftExpandPass(PR); - initializeAVRDAGToDAGISelPass(PR); + initializeAVRDAGToDAGISelLegacyPass(PR); } const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const { diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index bbdbdbb..694d7ba 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -35,7 +35,7 @@ InstructionSelector *createBPFInstructionSelector(const BPFTargetMachine &, const BPFRegisterBankInfo &); void initializeBPFCheckAndAdjustIRPass(PassRegistry&); -void initializeBPFDAGToDAGISelPass(PassRegistry &); +void initializeBPFDAGToDAGISelLegacyPass(PassRegistry &); void initializeBPFMIPeepholePass(PassRegistry &); void initializeBPFMIPreEmitCheckingPass(PassRegistry&); void initializeBPFMIPreEmitPeepholePass(PassRegistry &); diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp index 7b8bcb2..4cc209b 100644 --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -51,7 +51,7 @@ public: BPFDAGToDAGISel() = delete; explicit BPFDAGToDAGISel(BPFTargetMachine &TM) - : SelectionDAGISel(ID, TM), Subtarget(nullptr) {} + : SelectionDAGISel(TM), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. @@ -94,11 +94,18 @@ private: // Mapping from ConstantStruct global value to corresponding byte-list values std::map<const void *, val_vec_type> cs_vals_; }; + +class BPFDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + BPFDAGToDAGISelLegacy(BPFTargetMachine &TM) + : SelectionDAGISelLegacy(ID, std::make_unique<BPFDAGToDAGISel>(TM)) {} +}; } // namespace -char BPFDAGToDAGISel::ID = 0; +char BPFDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(BPFDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(BPFDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) // ComplexPattern used on BPF Load/Store instructions bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) { @@ -489,5 +496,5 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, } FunctionPass *llvm::createBPFISelDag(BPFTargetMachine &TM) { - return new BPFDAGToDAGISel(TM); + return new BPFDAGToDAGISelLegacy(TM); } diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index a7bed69..7b73c9f 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -48,7 +48,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() { initializeGlobalISel(PR); initializeBPFCheckAndAdjustIRPass(PR); initializeBPFMIPeepholePass(PR); - initializeBPFDAGToDAGISelPass(PR); + initializeBPFDAGToDAGISelLegacyPass(PR); } // DataLayout: little or big endian diff --git a/llvm/lib/Target/CSKY/CSKY.h b/llvm/lib/Target/CSKY/CSKY.h index 7ca630c..21ebf13 100644 --- a/llvm/lib/Target/CSKY/CSKY.h +++ b/llvm/lib/Target/CSKY/CSKY.h @@ -27,7 +27,7 @@ FunctionPass *createCSKYISelDag(CSKYTargetMachine &TM, FunctionPass *createCSKYConstantIslandPass(); void initializeCSKYConstantIslandsPass(PassRegistry &); -void initializeCSKYDAGToDAGISelPass(PassRegistry &); +void initializeCSKYDAGToDAGISelLegacyPass(PassRegistry &); } // namespace llvm diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp index c0c23a45..22da80b 100644 --- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp +++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp @@ -28,10 +28,8 @@ class CSKYDAGToDAGISel : public SelectionDAGISel { const CSKYSubtarget *Subtarget; public: - static char ID; - explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) {} + : SelectionDAGISel(TM, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { // Reset the subtarget each time through. @@ -54,11 +52,20 @@ public: #include "CSKYGenDAGISel.inc" }; + +class CSKYDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit CSKYDAGToDAGISelLegacy(CSKYTargetMachine &TM, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<CSKYDAGToDAGISel>(TM, OptLevel)) {} +}; } // namespace -char CSKYDAGToDAGISel::ID = 0; +char CSKYDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(CSKYDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) void CSKYDAGToDAGISel::Select(SDNode *N) { // If we have a custom node, we have already selected @@ -401,5 +408,5 @@ bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand( FunctionPass *llvm::createCSKYISelDag(CSKYTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new CSKYDAGToDAGISel(TM, OptLevel); + return new CSKYDAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp index 0bbfabe..a756061 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp @@ -30,7 +30,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTarget() { PassRegistry *Registry = PassRegistry::getPassRegistry(); initializeCSKYConstantIslandsPass(*Registry); - initializeCSKYDAGToDAGISelPass(*Registry); + initializeCSKYDAGToDAGISelLegacyPass(*Registry); } static std::string computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h index 861f61a..4a290c7 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.h +++ b/llvm/lib/Target/Hexagon/Hexagon.h @@ -22,7 +22,7 @@ namespace llvm { /// Creates a Hexagon-specific Target Transformation Info pass. ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM); - void initializeHexagonDAGToDAGISelPass(PassRegistry &); + void initializeHexagonDAGToDAGISelLegacyPass(PassRegistry &); } // end namespace llvm; #endif diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 6fe3fe0..febbc95 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -60,13 +60,18 @@ namespace llvm { /// Hexagon-specific DAG, ready for instruction scheduling. FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new HexagonDAGToDAGISel(TM, OptLevel); + return new HexagonDAGToDAGISelLegacy(TM, OptLevel); } } -char HexagonDAGToDAGISel::ID = 0; +HexagonDAGToDAGISelLegacy::HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<HexagonDAGToDAGISel>(tm, OptLevel)) {} -INITIALIZE_PASS(HexagonDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +char HexagonDAGToDAGISelLegacy::ID = 0; + +INITIALIZE_PASS(HexagonDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { SDValue Chain = LD->getChain(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index 50162b1..2d23aee 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -29,14 +29,13 @@ class HexagonDAGToDAGISel : public SelectionDAGISel { const HexagonSubtarget *HST; const HexagonInstrInfo *HII; const HexagonRegisterInfo *HRI; -public: - static char ID; +public: HexagonDAGToDAGISel() = delete; explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr), + : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr), HRI(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { @@ -162,6 +161,13 @@ private: SDValue balanceSubTree(SDNode *N, bool Factorize = false); void rebalanceAddressTrees(); }; // end HexagonDAGToDAGISel + +class HexagonDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm, + CodeGenOptLevel OptLevel); +}; } #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 3a792ec..e488650 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -254,7 +254,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() { initializeHexagonVectorCombineLegacyPass(PR); initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR); initializeHexagonVExtractPass(PR); - initializeHexagonDAGToDAGISelPass(PR); + initializeHexagonDAGToDAGISelLegacyPass(PR); } HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, diff --git a/llvm/lib/Target/Lanai/Lanai.h b/llvm/lib/Target/Lanai/Lanai.h index 0f87b17..72a7efc 100644 --- a/llvm/lib/Target/Lanai/Lanai.h +++ b/llvm/lib/Target/Lanai/Lanai.h @@ -37,7 +37,7 @@ FunctionPass *createLanaiMemAluCombinerPass(); // operations. FunctionPass *createLanaiSetflagAluCombinerPass(); -void initializeLanaiDAGToDAGISelPass(PassRegistry &); +void initializeLanaiDAGToDAGISelLegacyPass(PassRegistry &); } // namespace llvm diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp index 6f5495a..84b57d9 100644 --- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -53,11 +53,7 @@ public: LanaiDAGToDAGISel() = delete; explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine) - : SelectionDAGISel(ID, TargetMachine) {} - - bool runOnMachineFunction(MachineFunction &MF) override { - return SelectionDAGISel::runOnMachineFunction(MF); - } + : SelectionDAGISel(TargetMachine) {} bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode, @@ -97,11 +93,18 @@ bool canBeRepresentedAsSls(const ConstantSDNode &CN) { return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0); } +class LanaiDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit LanaiDAGToDAGISelLegacy(LanaiTargetMachine &TM) + : SelectionDAGISelLegacy(ID, std::make_unique<LanaiDAGToDAGISel>(TM)) {} +}; + } // namespace -char LanaiDAGToDAGISel::ID = 0; +char LanaiDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(LanaiDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(LanaiDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) // Helper functions for ComplexPattern used on LanaiInstrInfo // Used on Lanai Load/Store instructions. @@ -366,5 +369,5 @@ void LanaiDAGToDAGISel::selectFrameIndex(SDNode *Node) { // createLanaiISelDag - This pass converts a legalized DAG into a // Lanai-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createLanaiISelDag(LanaiTargetMachine &TM) { - return new LanaiDAGToDAGISel(TM); + return new LanaiDAGToDAGISelLegacy(TM); } diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index 2357221..68eb12f 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -37,7 +37,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget() { RegisterTargetMachine<LanaiTargetMachine> registered_target( getTheLanaiTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeLanaiDAGToDAGISelPass(PR); + initializeLanaiDAGToDAGISelLegacyPass(PR); } static std::string computeDataLayout() { diff --git a/llvm/lib/Target/LoongArch/LoongArch.h b/llvm/lib/Target/LoongArch/LoongArch.h index 2109176..0928ea3 100644 --- a/llvm/lib/Target/LoongArch/LoongArch.h +++ b/llvm/lib/Target/LoongArch/LoongArch.h @@ -38,7 +38,7 @@ FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM); FunctionPass *createLoongArchOptWInstrsPass(); FunctionPass *createLoongArchPreRAExpandPseudoPass(); FunctionPass *createLoongArchExpandPseudoPass(); -void initializeLoongArchDAGToDAGISelPass(PassRegistry &); +void initializeLoongArchDAGToDAGISelLegacyPass(PassRegistry &); void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &); void initializeLoongArchOptWInstrsPass(PassRegistry &); void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &); diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp index 726856b..b6ade6b 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp @@ -22,9 +22,14 @@ using namespace llvm; #define DEBUG_TYPE "loongarch-isel" #define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection" -char LoongArchDAGToDAGISel::ID; +char LoongArchDAGToDAGISelLegacy::ID; -INITIALIZE_PASS(LoongArchDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +LoongArchDAGToDAGISelLegacy::LoongArchDAGToDAGISelLegacy( + LoongArchTargetMachine &TM) + : SelectionDAGISelLegacy(ID, std::make_unique<LoongArchDAGToDAGISel>(TM)) {} + +INITIALIZE_PASS(LoongArchDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, + false) void LoongArchDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we have already selected. @@ -414,5 +419,5 @@ bool LoongArchDAGToDAGISel::selectVSplatUimmPow2(SDValue N, // This pass converts a legalized DAG into a LoongArch-specific DAG, ready // for instruction scheduling. FunctionPass *llvm::createLoongArchISelDag(LoongArchTargetMachine &TM) { - return new LoongArchDAGToDAGISel(TM); + return new LoongArchDAGToDAGISelLegacy(TM); } diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h index 48a178b..5c199a5 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h @@ -29,7 +29,7 @@ public: LoongArchDAGToDAGISel() = delete; explicit LoongArchDAGToDAGISel(LoongArchTargetMachine &TM) - : SelectionDAGISel(ID, TM) {} + : SelectionDAGISel(TM) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<LoongArchSubtarget>(); @@ -69,6 +69,12 @@ public: #include "LoongArchGenDAGISel.inc" }; +class LoongArchDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit LoongArchDAGToDAGISelLegacy(LoongArchTargetMachine &TM); +}; + } // end namespace llvm #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp index 2b2d4e4..83466d5 100644 --- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp @@ -36,7 +36,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTarget() { auto *PR = PassRegistry::getPassRegistry(); initializeLoongArchOptWInstrsPass(*PR); initializeLoongArchPreRAExpandPseudoPass(*PR); - initializeLoongArchDAGToDAGISelPass(*PR); + initializeLoongArchDAGToDAGISelLegacyPass(*PR); } static cl::opt<bool> diff --git a/llvm/lib/Target/M68k/M68k.h b/llvm/lib/Target/M68k/M68k.h index 1d0f383..5db9d79 100644 --- a/llvm/lib/Target/M68k/M68k.h +++ b/llvm/lib/Target/M68k/M68k.h @@ -46,7 +46,7 @@ InstructionSelector * createM68kInstructionSelector(const M68kTargetMachine &, const M68kSubtarget &, const M68kRegisterBankInfo &); -void initializeM68kDAGToDAGISelPass(PassRegistry &); +void initializeM68kDAGToDAGISelLegacyPass(PassRegistry &); void initializeM68kExpandPseudoPass(PassRegistry &); void initializeM68kGlobalBaseRegPass(PassRegistry &); void initializeM68kCollapseMOVEMPass(PassRegistry &); diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp index e3aa9cb..dc89fec 100644 --- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp +++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp @@ -174,12 +174,10 @@ namespace { class M68kDAGToDAGISel : public SelectionDAGISel { public: - static char ID; - M68kDAGToDAGISel() = delete; explicit M68kDAGToDAGISel(M68kTargetMachine &TM) - : SelectionDAGISel(ID, TM), Subtarget(nullptr) {} + : SelectionDAGISel(TM), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override; bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override; @@ -316,11 +314,18 @@ private: SDNode *getGlobalBaseReg(); }; -char M68kDAGToDAGISel::ID; +class M68kDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit M68kDAGToDAGISelLegacy(M68kTargetMachine &TM) + : SelectionDAGISelLegacy(ID, std::make_unique<M68kDAGToDAGISel>(TM)) {} +}; + +char M68kDAGToDAGISelLegacy::ID; } // namespace -INITIALIZE_PASS(M68kDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(M68kDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { @@ -357,7 +362,7 @@ bool M68kDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { /// This pass converts a legalized DAG into a M68k-specific DAG, /// ready for instruction scheduling. FunctionPass *llvm::createM68kISelDag(M68kTargetMachine &TM) { - return new M68kDAGToDAGISel(TM); + return new M68kDAGToDAGISelLegacy(TM); } static bool doesDispFitFI(M68kISelAddressMode &AM) { diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp index bbbcb15..b65de5e 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp +++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp @@ -37,7 +37,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTarget() { RegisterTargetMachine<M68kTargetMachine> X(getTheM68kTarget()); auto *PR = PassRegistry::getPassRegistry(); initializeGlobalISel(*PR); - initializeM68kDAGToDAGISelPass(*PR); + initializeM68kDAGToDAGISelLegacyPass(*PR); initializeM68kExpandPseudoPass(*PR); initializeM68kGlobalBaseRegPass(*PR); initializeM68kCollapseMOVEMPass(*PR); diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h index 60685b6..0198359 100644 --- a/llvm/lib/Target/MSP430/MSP430.h +++ b/llvm/lib/Target/MSP430/MSP430.h @@ -43,7 +43,7 @@ FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, FunctionPass *createMSP430BranchSelectionPass(); -void initializeMSP430DAGToDAGISelPass(PassRegistry &); +void initializeMSP430DAGToDAGISelLegacyPass(PassRegistry &); } // namespace llvm diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index efb23b1..7be51d9 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -91,12 +91,10 @@ namespace { namespace { class MSP430DAGToDAGISel : public SelectionDAGISel { public: - static char ID; - MSP430DAGToDAGISel() = delete; MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) {} + : SelectionDAGISel(TM, OptLevel) {} private: bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); @@ -119,18 +117,26 @@ namespace { bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp); }; + + class MSP430DAGToDAGISelLegacy : public SelectionDAGISelLegacy { + public: + static char ID; + MSP430DAGToDAGISelLegacy(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<MSP430DAGToDAGISel>(TM, OptLevel)) {} + }; } // end anonymous namespace -char MSP430DAGToDAGISel::ID; +char MSP430DAGToDAGISelLegacy::ID; -INITIALIZE_PASS(MSP430DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(MSP430DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) /// createMSP430ISelDag - This pass converts a legalized DAG into a /// MSP430-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new MSP430DAGToDAGISel(TM, OptLevel); + return new MSP430DAGToDAGISelLegacy(TM, OptLevel); } /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode. diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index ed0fcf7..f307c37 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -26,7 +26,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Target() { // Register the target. RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeMSP430DAGToDAGISelPass(PR); + initializeMSP430DAGToDAGISelLegacyPass(PR); } static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) { diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h index f0cf039..36a1733 100644 --- a/llvm/lib/Target/Mips/Mips.h +++ b/llvm/lib/Target/Mips/Mips.h @@ -47,7 +47,7 @@ InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &, void initializeMicroMipsSizeReducePass(PassRegistry &); void initializeMipsBranchExpansionPass(PassRegistry &); -void initializeMipsDAGToDAGISelPass(PassRegistry &); +void initializeMipsDAGToDAGISelLegacyPass(PassRegistry &); void initializeMipsDelaySlotFillerPass(PassRegistry &); void initializeMipsMulMulBugFixPass(PassRegistry &); void initializeMipsPostLegalizerCombinerPass(PassRegistry &); diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 0be9b94..b8e6dce 100644 --- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -219,7 +219,11 @@ bool Mips16DAGToDAGISel::trySelect(SDNode *Node) { return false; } +Mips16DAGToDAGISelLegacy::Mips16DAGToDAGISelLegacy(MipsTargetMachine &TM, + CodeGenOptLevel OL) + : MipsDAGToDAGISelLegacy(std::make_unique<Mips16DAGToDAGISel>(TM, OL)) {} + FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new Mips16DAGToDAGISel(TM, OptLevel); + return new Mips16DAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h index c6d3bde..ec6e745 100644 --- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h @@ -47,6 +47,11 @@ private: void initMips16SPAliasReg(MachineFunction &MF); }; +class Mips16DAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy { +public: + explicit Mips16DAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL); +}; + FunctionPass *createMips16ISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel); } diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index 01b41f3..f6f32fd 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -49,11 +49,11 @@ using namespace llvm; // instructions for SelectionDAG operations. //===----------------------------------------------------------------------===// -void MipsDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { +void MipsDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const { // There are multiple MipsDAGToDAGISel instances added to the pass pipeline. // We need to preserve StackProtector for the next one. AU.addPreserved<StackProtector>(); - SelectionDAGISel::getAnalysisUsage(AU); + SelectionDAGISelLegacy::getAnalysisUsage(AU); } bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { @@ -344,6 +344,10 @@ bool MipsDAGToDAGISel::isUnneededShiftMask(SDNode *N, return (Known.Zero | RHS).countr_one() >= ShAmtBits; } -char MipsDAGToDAGISel::ID = 0; +char MipsDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(MipsDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +MipsDAGToDAGISelLegacy::MipsDAGToDAGISelLegacy( + std::unique_ptr<SelectionDAGISel> S) + : SelectionDAGISelLegacy(ID, std::move(S)) {} + +INITIALIZE_PASS(MipsDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h index 52207d0..6135f96 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.h @@ -30,17 +30,13 @@ namespace llvm { class MipsDAGToDAGISel : public SelectionDAGISel { public: - static char ID; - MipsDAGToDAGISel() = delete; explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL) - : SelectionDAGISel(ID, TM, OL), Subtarget(nullptr) {} + : SelectionDAGISel(TM, OL), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override; - void getAnalysisUsage(AnalysisUsage &AU) const override; - protected: SDNode *getGlobalBaseReg(); @@ -145,6 +141,13 @@ private: std::vector<SDValue> &OutOps) override; bool isUnneededShiftMask(SDNode *N, unsigned ShAmtBits) const; }; + +class MipsDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + MipsDAGToDAGISelLegacy(std::unique_ptr<SelectionDAGISel> S); + void getAnalysisUsage(AnalysisUsage &AU) const override; +}; } #endif diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index ab39d1b..7ad300c 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -44,9 +44,9 @@ bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { return MipsDAGToDAGISel::runOnMachineFunction(MF); } -void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { +void MipsSEDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<DominatorTreeWrapperPass>(); - SelectionDAGISel::getAnalysisUsage(AU); + SelectionDAGISelLegacy::getAnalysisUsage(AU); } void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, @@ -1439,7 +1439,11 @@ bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand( return true; } +MipsSEDAGToDAGISelLegacy::MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM, + CodeGenOptLevel OL) + : MipsDAGToDAGISelLegacy(std::make_unique<MipsSEDAGToDAGISel>(TM, OL)) {} + FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new MipsSEDAGToDAGISel(TM, OptLevel); + return new MipsSEDAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h index 96dc876..7b843b0 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h @@ -27,8 +27,6 @@ private: bool runOnMachineFunction(MachineFunction &MF) override; - void getAnalysisUsage(AnalysisUsage &AU) const override; - void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, MachineFunction &MF); @@ -139,6 +137,12 @@ private: std::vector<SDValue> &OutOps) override; }; +class MipsSEDAGToDAGISelLegacy : public MipsDAGToDAGISelLegacy { +public: + explicit MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL); + void getAnalysisUsage(AnalysisUsage &AU) const override; +}; + FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel); } diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 4c4bf70..9515e50 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -67,7 +67,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { initializeMipsPreLegalizerCombinerPass(*PR); initializeMipsPostLegalizerCombinerPass(*PR); initializeMipsMulMulBugFixPass(*PR); - initializeMipsDAGToDAGISelPass(*PR); + initializeMipsDAGToDAGISelLegacyPass(*PR); } static std::string computeDataLayout(const Triple &TT, StringRef CPU, diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h index 07ee349..5eefab5 100644 --- a/llvm/lib/Target/NVPTX/NVPTX.h +++ b/llvm/lib/Target/NVPTX/NVPTX.h @@ -194,7 +194,7 @@ enum PrmtMode { }; } } -void initializeNVPTXDAGToDAGISelPass(PassRegistry &); +void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &); } // namespace llvm // Defines symbolic names for NVPTX registers. This defines a mapping from diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index 2713b68..1e1cbb1 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -38,16 +38,21 @@ static cl::opt<bool> /// NVPTX-specific DAG, ready for instruction scheduling. FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOptLevel OptLevel) { - return new NVPTXDAGToDAGISel(TM, OptLevel); + return new NVPTXDAGToDAGISelLegacy(TM, OptLevel); } -char NVPTXDAGToDAGISel::ID = 0; +NVPTXDAGToDAGISelLegacy::NVPTXDAGToDAGISelLegacy(NVPTXTargetMachine &tm, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<NVPTXDAGToDAGISel>(tm, OptLevel)) {} -INITIALIZE_PASS(NVPTXDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +char NVPTXDAGToDAGISelLegacy::ID = 0; + +INITIALIZE_PASS(NVPTXDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, tm, OptLevel), TM(tm) { + : SelectionDAGISel(tm, OptLevel), TM(tm) { doMulWide = (OptLevel > CodeGenOptLevel::None); } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h index 7a77747..c552435 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h @@ -39,8 +39,6 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel { bool doRsqrtOpt() const; public: - static char ID; - NVPTXDAGToDAGISel() = delete; explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOptLevel OptLevel); @@ -101,6 +99,13 @@ private: static unsigned GetConvertOpcode(MVT DestTy, MVT SrcTy, LoadSDNode *N); }; + +class NVPTXDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit NVPTXDAGToDAGISelLegacy(NVPTXTargetMachine &tm, + CodeGenOptLevel OptLevel); +}; } // end namespace llvm #endif diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 2a47c16..4dc3cea 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -103,7 +103,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() { initializeNVPTXCtorDtorLoweringLegacyPass(PR); initializeNVPTXLowerAggrCopiesPass(PR); initializeNVPTXProxyRegErasurePass(PR); - initializeNVPTXDAGToDAGISelPass(PR); + initializeNVPTXDAGToDAGISelLegacyPass(PR); initializeNVPTXAAWrapperPassPass(PR); initializeNVPTXExternalAAWrapperPass(PR); } diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index eb8886d..94a59d1 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -78,7 +78,7 @@ class ModulePass; void initializePPCMIPeepholePass(PassRegistry&); void initializePPCExpandAtomicPseudoPass(PassRegistry &); void initializePPCCTRLoopsPass(PassRegistry &); - void initializePPCDAGToDAGISelPass(PassRegistry &); + void initializePPCDAGToDAGISelLegacyPass(PassRegistry &); void initializePPCMergeStringPoolPass(PassRegistry &); extern char &PPCVSXFMAMutateID; diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 26560dc..275b333 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -147,12 +147,10 @@ namespace { unsigned GlobalBaseReg = 0; public: - static char ID; - PPCDAGToDAGISel() = delete; explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {} + : SelectionDAGISel(tm, OptLevel), TM(tm) {} bool runOnMachineFunction(MachineFunction &MF) override { // Make sure we re-emit a set of the global base reg if necessary @@ -447,11 +445,19 @@ private: void transferMemOperands(SDNode *N, SDNode *Result); }; + class PPCDAGToDAGISelLegacy : public SelectionDAGISelLegacy { + public: + static char ID; + explicit PPCDAGToDAGISelLegacy(PPCTargetMachine &tm, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<PPCDAGToDAGISel>(tm, OptLevel)) {} + }; } // end anonymous namespace -char PPCDAGToDAGISel::ID = 0; +char PPCDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(PPCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(PPCDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. @@ -7921,5 +7927,5 @@ void PPCDAGToDAGISel::PeepholePPC64() { /// FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new PPCDAGToDAGISel(TM, OptLevel); + return new PPCDAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 714cf69..1ef891d 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -141,7 +141,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() { initializePPCExpandAtomicPseudoPass(PR); initializeGlobalISel(PR); initializePPCCTRLoopsPass(PR); - initializePPCDAGToDAGISelPass(PR); + initializePPCDAGToDAGISelLegacyPass(PR); initializePPCMergeStringPoolPass(PR); } diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h index dcf4c65..8d2e1fc 100644 --- a/llvm/lib/Target/RISCV/RISCV.h +++ b/llvm/lib/Target/RISCV/RISCV.h @@ -82,7 +82,7 @@ void initializeRISCVPushPopOptPass(PassRegistry &); InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &); -void initializeRISCVDAGToDAGISelPass(PassRegistry &); +void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &); FunctionPass *createRISCVPostLegalizerCombiner(); void initializeRISCVPostLegalizerCombinerPass(PassRegistry &); diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index d965dd4..251401d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -3912,9 +3912,14 @@ bool RISCVDAGToDAGISel::doPeepholeNoRegPassThru() { // for instruction scheduling. FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new RISCVDAGToDAGISel(TM, OptLevel); + return new RISCVDAGToDAGISelLegacy(TM, OptLevel); } -char RISCVDAGToDAGISel::ID = 0; +char RISCVDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +RISCVDAGToDAGISelLegacy::RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TM, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<RISCVDAGToDAGISel>(TM, OptLevel)) {} + +INITIALIZE_PASS(RISCVDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index ece04dd..5d70245 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -25,13 +25,11 @@ class RISCVDAGToDAGISel : public SelectionDAGISel { const RISCVSubtarget *Subtarget = nullptr; public: - static char ID; - RISCVDAGToDAGISel() = delete; explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TargetMachine, OptLevel) {} + : SelectionDAGISel(TargetMachine, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<RISCVSubtarget>(); @@ -196,6 +194,13 @@ private: bool performCombineVMergeAndVOps(SDNode *N); }; +class RISCVDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TargetMachine, + CodeGenOptLevel OptLevel); +}; + namespace RISCV { struct VLSEGPseudo { uint16_t NF : 4; diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 87ae2ee..35d0b34 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -123,7 +123,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { initializeRISCVInsertVSETVLIPass(*PR); initializeRISCVInsertReadWriteCSRPass(*PR); initializeRISCVInsertWriteVXRMPass(*PR); - initializeRISCVDAGToDAGISelPass(*PR); + initializeRISCVDAGToDAGISelLegacyPass(*PR); initializeRISCVMoveMergePass(*PR); initializeRISCVPushPopOptPass(*PR); } diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h index fca7657..33a8034 100644 --- a/llvm/lib/Target/Sparc/Sparc.h +++ b/llvm/lib/Target/Sparc/Sparc.h @@ -31,7 +31,7 @@ FunctionPass *createSparcDelaySlotFillerPass(); void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); -void initializeSparcDAGToDAGISelPass(PassRegistry &); +void initializeSparcDAGToDAGISelLegacyPass(PassRegistry &); } // namespace llvm namespace llvm { diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 3c9841d..2531611 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -35,12 +35,11 @@ class SparcDAGToDAGISel : public SelectionDAGISel { /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can /// make the right decision when generating code for different targets. const SparcSubtarget *Subtarget = nullptr; -public: - static char ID; +public: SparcDAGToDAGISel() = delete; - explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(ID, tm) {} + explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<SparcSubtarget>(); @@ -66,11 +65,18 @@ private: SDNode* getGlobalBaseReg(); bool tryInlineAsm(SDNode *N); }; + +class SparcDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit SparcDAGToDAGISelLegacy(SparcTargetMachine &tm) + : SelectionDAGISelLegacy(ID, std::make_unique<SparcDAGToDAGISel>(tm)) {} +}; } // end anonymous namespace -char SparcDAGToDAGISel::ID = 0; +char SparcDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(SparcDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(SparcDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) SDNode* SparcDAGToDAGISel::getGlobalBaseReg() { Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); @@ -397,5 +403,5 @@ bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand( /// SPARC-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) { - return new SparcDAGToDAGISel(TM); + return new SparcDAGToDAGISelLegacy(TM); } diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 20ddafb0..ea40323 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -28,7 +28,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeSparcDAGToDAGISelPass(PR); + initializeSparcDAGToDAGISelLegacyPass(PR); } static cl::opt<bool> diff --git a/llvm/lib/Target/SystemZ/SystemZ.h b/llvm/lib/Target/SystemZ/SystemZ.h index d7aa9e4..8824954 100644 --- a/llvm/lib/Target/SystemZ/SystemZ.h +++ b/llvm/lib/Target/SystemZ/SystemZ.h @@ -199,7 +199,7 @@ FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM); FunctionPass *createSystemZTDCPass(); void initializeSystemZCopyPhysRegsPass(PassRegistry &); -void initializeSystemZDAGToDAGISelPass(PassRegistry &); +void initializeSystemZDAGToDAGISelLegacyPass(PassRegistry &); void initializeSystemZElimComparePass(PassRegistry &); void initializeSystemZLDCleanupPass(PassRegistry &); void initializeSystemZLongBranchPass(PassRegistry &); diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 1bf23c2..6c6a9b4 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -356,12 +356,10 @@ class SystemZDAGToDAGISel : public SelectionDAGISel { bool shouldSelectForReassoc(SDNode *N) const; public: - static char ID; - SystemZDAGToDAGISel() = delete; SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) {} + : SelectionDAGISel(TM, OptLevel) {} bool runOnMachineFunction(MachineFunction &MF) override { const Function &F = MF.getFunction(); @@ -387,15 +385,24 @@ public: // Include the pieces autogenerated from the target description. #include "SystemZGenDAGISel.inc" }; + +class SystemZDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit SystemZDAGToDAGISelLegacy(SystemZTargetMachine &TM, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<SystemZDAGToDAGISel>(TM, OptLevel)) {} +}; } // end anonymous namespace -char SystemZDAGToDAGISel::ID = 0; +char SystemZDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(SystemZDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(SystemZDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new SystemZDAGToDAGISel(TM, OptLevel); + return new SystemZDAGToDAGISelLegacy(TM, OptLevel); } // Return true if Val should be selected as a displacement for an address diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index dced64d..6f76839 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -47,7 +47,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() { initializeSystemZShortenInstPass(PR); initializeSystemZPostRewritePass(PR); initializeSystemZTDCPassPass(PR); - initializeSystemZDAGToDAGISelPass(PR); + initializeSystemZDAGToDAGISelLegacyPass(PR); } static std::string computeDataLayout(const Triple &TT) { diff --git a/llvm/lib/Target/VE/VE.h b/llvm/lib/Target/VE/VE.h index 6f024301..ee76c51 100644 --- a/llvm/lib/Target/VE/VE.h +++ b/llvm/lib/Target/VE/VE.h @@ -29,7 +29,7 @@ class VETargetMachine; FunctionPass *createVEISelDag(VETargetMachine &TM); FunctionPass *createLVLGenPass(); -void initializeVEDAGToDAGISelPass(PassRegistry &); +void initializeVEDAGToDAGISelLegacyPass(PassRegistry &); void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp index 87646bc..680bd12 100644 --- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp +++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp @@ -34,11 +34,9 @@ class VEDAGToDAGISel : public SelectionDAGISel { const VESubtarget *Subtarget; public: - static char ID; - VEDAGToDAGISel() = delete; - explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {} + explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {} bool runOnMachineFunction(MachineFunction &MF) override { Subtarget = &MF.getSubtarget<VESubtarget>(); @@ -70,11 +68,18 @@ private: bool matchADDRrr(SDValue N, SDValue &Base, SDValue &Index); bool matchADDRri(SDValue N, SDValue &Base, SDValue &Offset); }; + +class VEDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit VEDAGToDAGISelLegacy(VETargetMachine &tm) + : SelectionDAGISelLegacy(ID, std::make_unique<VEDAGToDAGISel>(tm)) {} +}; } // end anonymous namespace -char VEDAGToDAGISel::ID = 0; +char VEDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(VEDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(VEDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Offset) { @@ -336,5 +341,5 @@ SDNode *VEDAGToDAGISel::getGlobalBaseReg() { /// VE-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) { - return new VEDAGToDAGISel(TM); + return new VEDAGToDAGISelLegacy(TM); } diff --git a/llvm/lib/Target/VE/VETargetMachine.cpp b/llvm/lib/Target/VE/VETargetMachine.cpp index 6f4e137..383667b 100644 --- a/llvm/lib/Target/VE/VETargetMachine.cpp +++ b/llvm/lib/Target/VE/VETargetMachine.cpp @@ -30,7 +30,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() { RegisterTargetMachine<VETargetMachine> X(getTheVETarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeVEDAGToDAGISelPass(PR); + initializeVEDAGToDAGISelLegacyPass(PR); } static std::string computeDataLayout(const Triple &T) { diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h index 7fc8546..8f142fa 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.h +++ b/llvm/lib/Target/WebAssembly/WebAssembly.h @@ -67,7 +67,7 @@ void initializeWebAssemblyArgumentMovePass(PassRegistry &); void initializeWebAssemblyCleanCodeAfterTrapPass(PassRegistry &); void initializeWebAssemblyCFGSortPass(PassRegistry &); void initializeWebAssemblyCFGStackifyPass(PassRegistry &); -void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &); +void initializeWebAssemblyDAGToDAGISelLegacyPass(PassRegistry &); void initializeWebAssemblyDebugFixupPass(PassRegistry &); void initializeWebAssemblyExceptionInfoPass(PassRegistry &); void initializeWebAssemblyExplicitLocalsPass(PassRegistry &); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp index 8833aee..0f06f54 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp @@ -42,13 +42,11 @@ class WebAssemblyDAGToDAGISel final : public SelectionDAGISel { const WebAssemblySubtarget *Subtarget; public: - static char ID; - WebAssemblyDAGToDAGISel() = delete; WebAssemblyDAGToDAGISel(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel), Subtarget(nullptr) {} + : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {} bool runOnMachineFunction(MachineFunction &MF) override { LLVM_DEBUG(dbgs() << "********** ISelDAGToDAG **********\n" @@ -82,11 +80,21 @@ private: bool SelectAddrAddOperands(MVT OffsetType, SDValue N, SDValue &Offset, SDValue &Addr); }; + +class WebAssemblyDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + explicit WebAssemblyDAGToDAGISelLegacy(WebAssemblyTargetMachine &TM, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<WebAssemblyDAGToDAGISel>(TM, OptLevel)) {} +}; } // end anonymous namespace -char WebAssemblyDAGToDAGISel::ID; +char WebAssemblyDAGToDAGISelLegacy::ID; -INITIALIZE_PASS(WebAssemblyDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(WebAssemblyDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, + false) void WebAssemblyDAGToDAGISel::PreprocessISelDAG() { // Stack objects that should be allocated to locals are hoisted to WebAssembly @@ -409,5 +417,5 @@ bool WebAssemblyDAGToDAGISel::SelectAddrOperands64(SDValue Op, SDValue &Offset, /// for instruction scheduling. FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new WebAssemblyDAGToDAGISel(TM, OptLevel); + return new WebAssemblyDAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index fd92a35..23539a5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -90,7 +90,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget() { initializeWebAssemblyMCLowerPrePassPass(PR); initializeWebAssemblyLowerRefTypesIntPtrConvPass(PR); initializeWebAssemblyFixBrTableDefaultsPass(PR); - initializeWebAssemblyDAGToDAGISelPass(PR); + initializeWebAssemblyDAGToDAGISelLegacyPass(PR); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h index 21623a8..fdb9e4c 100644 --- a/llvm/lib/Target/X86/X86.h +++ b/llvm/lib/Target/X86/X86.h @@ -179,7 +179,7 @@ void initializeX86AvoidSFBPassPass(PassRegistry &); void initializeX86AvoidTrailingCallPassPass(PassRegistry &); void initializeX86CallFrameOptimizationPass(PassRegistry &); void initializeX86CmovConverterPassPass(PassRegistry &); -void initializeX86DAGToDAGISelPass(PassRegistry &); +void initializeX86DAGToDAGISelLegacyPass(PassRegistry &); void initializeX86DomainReassignmentPass(PassRegistry &); void initializeX86ExecutionDomainFixPass(PassRegistry &); void initializeX86ExpandPseudoPass(PassRegistry &); diff --git a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp index 7c1fb0b..cc5937d 100644 --- a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp +++ b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp @@ -10,10 +10,12 @@ /// TODO: Port CodeGen passes to new pass manager. //===----------------------------------------------------------------------===// +#include "X86ISelDAGToDAG.h" #include "X86TargetMachine.h" #include "llvm/MC/MCStreamer.h" #include "llvm/Passes/CodeGenPassBuilder.h" +#include "llvm/Passes/PassBuilder.h" using namespace llvm; @@ -40,13 +42,20 @@ void X86CodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass, // TODO: Add AsmPrinter. } -Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &) const { +Error X86CodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const { // TODO: Add instruction selector. + addPass(X86ISelDAGToDAGPass(static_cast<X86TargetMachine &>(TM))); return Error::success(); } } // namespace +void X86TargetMachine::registerPassBuilderCallbacks( + PassBuilder &PB, bool PopulateClassToPassNames) { +#define GET_PASS_REGISTRY "X86PassRegistry.def" +#include "llvm/Passes/TargetPassRegistry.inc" +} + Error X86TargetMachine::buildCodeGenPipeline( ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, const CGPassBuilderOption &Opt, diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 3227bf7..0bf3294 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +#include "X86ISelDAGToDAG.h" #include "X86.h" #include "X86MachineFunctionInfo.h" #include "X86RegisterInfo.h" @@ -169,12 +170,10 @@ namespace { bool IndirectTlsSegRefs; public: - static char ID; - X86DAGToDAGISel() = delete; explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr), + : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr), OptForMinSize(false), IndirectTlsSegRefs(false) {} bool runOnMachineFunction(MachineFunction &MF) override { @@ -187,9 +186,7 @@ namespace { OptForMinSize = MF.getFunction().hasMinSize(); assert((!OptForMinSize || MF.getFunction().hasOptSize()) && "OptForMinSize implies OptForSize"); - - SelectionDAGISel::runOnMachineFunction(MF); - return true; + return SelectionDAGISel::runOnMachineFunction(MF); } void emitFunctionEntryCode() override; @@ -577,11 +574,20 @@ namespace { bool hasNoSignFlagUses(SDValue Flags) const; bool hasNoCarryFlagUses(SDValue Flags) const; }; + + class X86DAGToDAGISelLegacy : public SelectionDAGISelLegacy { + public: + static char ID; + explicit X86DAGToDAGISelLegacy(X86TargetMachine &tm, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<X86DAGToDAGISel>(tm, OptLevel)) {} + }; } -char X86DAGToDAGISel::ID = 0; +char X86DAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(X86DAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(X86DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) // Returns true if this masked compare can be implemented legally with this // type. @@ -6593,9 +6599,13 @@ bool X86DAGToDAGISel::SelectInlineAsmMemoryOperand( return false; } +X86ISelDAGToDAGPass::X86ISelDAGToDAGPass(X86TargetMachine &TM) + : SelectionDAGISelPass( + std::make_unique<X86DAGToDAGISel>(TM, TM.getOptLevel())) {} + /// This pass converts a legalized DAG into a X86-specific DAG, /// ready for instruction scheduling. FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel) { - return new X86DAGToDAGISel(TM, OptLevel); + return new X86DAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.h b/llvm/lib/Target/X86/X86ISelDAGToDAG.h new file mode 100644 index 0000000..1f30c25b --- /dev/null +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.h @@ -0,0 +1,25 @@ +//===-- X86ISelDAGToDAG.h ---------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H +#define LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H + +#include "llvm/CodeGen/SelectionDAGISel.h" + +namespace llvm { + +class X86TargetMachine; + +class X86ISelDAGToDAGPass : public SelectionDAGISelPass { +public: + X86ISelDAGToDAGPass(X86TargetMachine &TM); +}; + +} // namespace llvm + +#endif // LLVM_LIB_TARGET_X86_X86ISELDAGTODAG_H diff --git a/llvm/lib/Target/X86/X86PassRegistry.def b/llvm/lib/Target/X86/X86PassRegistry.def new file mode 100644 index 0000000..620526ff --- /dev/null +++ b/llvm/lib/Target/X86/X86PassRegistry.def @@ -0,0 +1,19 @@ +//===- X86PassRegistry.def - Registry of X86 specific passes ----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is used as the registry of passes that are part of the X86 backend. +// +//===----------------------------------------------------------------------===// + +// NOTE: NO INCLUDE GUARD DESIRED! + +#ifndef MACHINE_FUNCTION_PASS +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) +#endif +MACHINE_FUNCTION_PASS("x86-isel", X86ISelDAGToDAGPass(*this)) +#undef MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index ab59cf8..27542e5 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -100,7 +100,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() { initializeX86PartialReductionPass(PR); initializePseudoProbeInserterPass(PR); initializeX86ReturnThunksPass(PR); - initializeX86DAGToDAGISelPass(PR); + initializeX86DAGToDAGISelLegacyPass(PR); initializeX86ArgumentStackSlotPassPass(PR); initializeX86FixupInstTuningPassPass(PR); initializeX86FixupVectorConstantsPassPass(PR); diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 4e7ded1..4a5f20f 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -58,6 +58,9 @@ public: createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override; + void registerPassBuilderCallbacks(PassBuilder &PB, + bool PopulateClassToPassNames) override; + Error buildCodeGenPipeline(ModulePassManager &, raw_pwrite_stream &, raw_pwrite_stream *, CodeGenFileType, const CGPassBuilderOption &, diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h index f019fa4..ad50f05 100644 --- a/llvm/lib/Target/XCore/XCore.h +++ b/llvm/lib/Target/XCore/XCore.h @@ -31,7 +31,7 @@ namespace llvm { FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel); ModulePass *createXCoreLowerThreadLocalPass(); - void initializeXCoreDAGToDAGISelPass(PassRegistry &); + void initializeXCoreDAGToDAGISelLegacyPass(PassRegistry &); } // end namespace llvm; diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 1535eb6..dcbf114 100644 --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -41,12 +41,10 @@ namespace { class XCoreDAGToDAGISel : public SelectionDAGISel { public: - static char ID; - XCoreDAGToDAGISel() = delete; XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) {} + : SelectionDAGISel(TM, OptLevel) {} void Select(SDNode *N) override; bool tryBRIND(SDNode *N); @@ -78,18 +76,27 @@ namespace { // Include the pieces autogenerated from the target description. #include "XCoreGenDAGISel.inc" }; + + class XCoreDAGToDAGISelLegacy : public SelectionDAGISelLegacy { + public: + static char ID; + explicit XCoreDAGToDAGISelLegacy(XCoreTargetMachine &TM, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<XCoreDAGToDAGISel>(TM, OptLevel)) {} + }; } // end anonymous namespace -char XCoreDAGToDAGISel::ID = 0; +char XCoreDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(XCoreDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(XCoreDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) /// createXCoreISelDag - This pass converts a legalized DAG into a /// XCore-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new XCoreDAGToDAGISel(TM, OptLevel); + return new XCoreDAGToDAGISelLegacy(TM, OptLevel); } bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index 374e91d..bb5beef 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -107,7 +107,7 @@ void XCorePassConfig::addPreEmitPass() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreTarget() { RegisterTargetMachine<XCoreTargetMachine> X(getTheXCoreTarget()); PassRegistry &PR = *PassRegistry::getPassRegistry(); - initializeXCoreDAGToDAGISelPass(PR); + initializeXCoreDAGToDAGISelLegacyPass(PR); } TargetTransformInfo diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 5ebedef..145f285 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -28,14 +28,8 @@ namespace { class XtensaDAGToDAGISel : public SelectionDAGISel { public: - static char ID; - XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, TM, OptLevel) {} - - StringRef getPassName() const override { - return "Xtensa DAG->DAG Pattern Instruction Selection"; - } + : SelectionDAGISel(TM, OptLevel) {} void Select(SDNode *Node) override; @@ -107,13 +101,26 @@ public: // Include the pieces autogenerated from the target description. #include "XtensaGenDAGISel.inc" }; // namespace + +class XtensaDAGToDAGISelLegacy : public SelectionDAGISelLegacy { +public: + static char ID; + + XtensaDAGToDAGISelLegacy(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<XtensaDAGToDAGISel>(TM, OptLevel)) {} + + StringRef getPassName() const override { + return "Xtensa DAG->DAG Pattern Instruction Selection"; + } +}; } // end anonymous namespace -char XtensaDAGToDAGISel::ID = 0; +char XtensaDAGToDAGISelLegacy::ID = 0; FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new XtensaDAGToDAGISel(TM, OptLevel); + return new XtensaDAGToDAGISelLegacy(TM, OptLevel); } void XtensaDAGToDAGISel::Select(SDNode *Node) { |