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author | Luke Lau <luke@igalia.com> | 2025-07-25 12:34:09 +0800 |
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committer | GitHub <noreply@github.com> | 2025-07-25 12:34:09 +0800 |
commit | 4b1ca9c072cc36af77afecbc95be3c3c3e764404 (patch) | |
tree | 3eff3dd2b2a4acddf47a6c4e37b2310d18981a0d /llvm/lib/Target | |
parent | 4bee7e09dfabf326ead941067a9ce9975f768918 (diff) | |
download | llvm-4b1ca9c072cc36af77afecbc95be3c3c3e764404.zip llvm-4b1ca9c072cc36af77afecbc95be3c3c3e764404.tar.gz llvm-4b1ca9c072cc36af77afecbc95be3c3c3e764404.tar.bz2 |
[RISCV] Remove -riscv-enable-vl-optimizer flag (#149349)
The RISCVVLOptimizer has been enabled by default for a while now and I'm
not aware of any outstanding issues that might need it to be disabled.
This removes the -riscv-enable-vl-optimizer flag to reduce the number of
configurations we have to support.
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index b43b915..da6ac2f 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -104,11 +104,6 @@ static cl::opt<bool> EnablePostMISchedLoadStoreClustering( cl::desc("Enable PostRA load and store clustering in the machine scheduler"), cl::init(true)); -static cl::opt<bool> - EnableVLOptimizer("riscv-enable-vl-optimizer", - cl::desc("Enable the RISC-V VL Optimizer pass"), - cl::init(true), cl::Hidden); - static cl::opt<bool> DisableVectorMaskMutation( "riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), @@ -617,8 +612,7 @@ void RISCVPassConfig::addPreRegAlloc() { addPass(createRISCVPreRAExpandPseudoPass()); if (TM->getOptLevel() != CodeGenOptLevel::None) { addPass(createRISCVMergeBaseOffsetOptPass()); - if (EnableVLOptimizer) - addPass(createRISCVVLOptimizerPass()); + addPass(createRISCVVLOptimizerPass()); } addPass(createRISCVInsertReadWriteCSRPass()); |