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| author | Ben Shi <2283975856@qq.com> | 2023-06-11 08:41:44 +0800 |
|---|---|---|
| committer | Ben Shi <2283975856@qq.com> | 2023-06-11 08:41:47 +0800 |
| commit | 71d90f310867c78532c5bdb9ba553859910ee67e (patch) | |
| tree | d9846606030eede4d97b0b0934437c59becf59a8 /llvm/lib/Target/AVR | |
| parent | e21df8296d09aff68039520ca1ab7dc4907922a2 (diff) | |
| download | llvm-71d90f310867c78532c5bdb9ba553859910ee67e.zip llvm-71d90f310867c78532c5bdb9ba553859910ee67e.tar.gz llvm-71d90f310867c78532c5bdb9ba553859910ee67e.tar.bz2 | |
[AVR] Optimize 8-bit rotation when rotation bits == 3
Fixes https://github.com/llvm/llvm-project/issues/63100
Reviewed By: aykevl
Differential Revision: https://reviews.llvm.org/D152365
Diffstat (limited to 'llvm/lib/Target/AVR')
| -rw-r--r-- | llvm/lib/Target/AVR/AVRISelLowering.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index d0314fb..ee0693c 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -427,6 +427,18 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, DAG.getConstant(7, dl, VT)); ShiftAmount = 0; + } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) { + // Optimize left rotation 3 bits to swap then right rotation 1 bit. + Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); + Victim = + DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT)); + ShiftAmount = 0; + } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 3) { + // Optimize right rotation 3 bits to swap then left rotation 1 bit. + Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); + Victim = + DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT)); + ShiftAmount = 0; } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) { // Optimize left rotation 7 bits to right rotation 1 bit. Victim = |