diff options
| -rw-r--r-- | llvm/lib/Target/AVR/AVRISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AVR/rotate.ll | 22 |
2 files changed, 19 insertions, 15 deletions
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index d0314fb..ee0693c 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -427,6 +427,18 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, DAG.getConstant(7, dl, VT)); ShiftAmount = 0; + } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) { + // Optimize left rotation 3 bits to swap then right rotation 1 bit. + Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); + Victim = + DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT)); + ShiftAmount = 0; + } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 3) { + // Optimize right rotation 3 bits to swap then left rotation 1 bit. + Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); + Victim = + DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT)); + ShiftAmount = 0; } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) { // Optimize left rotation 7 bits to right rotation 1 bit. Victim = diff --git a/llvm/test/CodeGen/AVR/rotate.ll b/llvm/test/CodeGen/AVR/rotate.ll index 938b64f..79ff792 100644 --- a/llvm/test/CodeGen/AVR/rotate.ll +++ b/llvm/test/CodeGen/AVR/rotate.ll @@ -15,12 +15,10 @@ start: define i8 @rotl8_3(i8 %x) { ; CHECK-LABEL: rotl8_3: ; CHECK: ; %bb.0: ; %start -; CHECK-NEXT: lsl r24 -; CHECK-NEXT: adc r24, r1 -; CHECK-NEXT: lsl r24 -; CHECK-NEXT: adc r24, r1 -; CHECK-NEXT: lsl r24 -; CHECK-NEXT: adc r24, r1 +; CHECK-NEXT: swap r24 +; CHECK-NEXT: bst r24, 0 +; CHECK-NEXT: ror r24 +; CHECK-NEXT: bld r24, 7 ; CHECK-NEXT: ret start: %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3) @@ -85,15 +83,9 @@ start: define i8 @rotr8_3(i8 %x) { ; CHECK-LABEL: rotr8_3: ; CHECK: ; %bb.0: ; %start -; CHECK-NEXT: bst r24, 0 -; CHECK-NEXT: ror r24 -; CHECK-NEXT: bld r24, 7 -; CHECK-NEXT: bst r24, 0 -; CHECK-NEXT: ror r24 -; CHECK-NEXT: bld r24, 7 -; CHECK-NEXT: bst r24, 0 -; CHECK-NEXT: ror r24 -; CHECK-NEXT: bld r24, 7 +; CHECK-NEXT: swap r24 +; CHECK-NEXT: lsl r24 +; CHECK-NEXT: adc r24, r1 ; CHECK-NEXT: ret start: %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3) |