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authorsstwcw <f0gukp2nk@protonmail.com>2022-06-26 01:54:02 +0000
committersstwcw <f0gukp2nk@protonmail.com>2022-06-26 02:02:29 +0000
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treebe287878ca225b6985624c1dc1b1ac918f317c10 /llvm/lib/Support/Process.cpp
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[clang-format] Handle Verilog preprocessor directives
Verilog uses the backtick instead of the hash. In this revision backticks are lexed manually and then get labeled as hashes so the logic for handling C preprocessor stuff don't have to change. Hashes get labeled as identifiers for Verilog-specific stuff like delays. Reviewed By: HazardyKnusperkeks Differential Revision: https://reviews.llvm.org/D124749
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