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author | Fabian Ritter <fabian.ritter@amd.com> | 2025-07-30 13:01:23 +0200 |
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committer | GitHub <noreply@github.com> | 2025-07-30 13:01:23 +0200 |
commit | ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4 (patch) | |
tree | 3ca40086ceb1b6fe38f2d7caf3f8db5df2a91980 /llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | |
parent | 8a09adc22adb18387e7c40db076af32b394db288 (diff) | |
download | llvm-ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4.zip llvm-ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4.tar.gz llvm-ef6eaa045aaa20c8c01d35c02b6200b3be5d5bb4.tar.bz2 |
[GISel] Introduce MIFlags::InBounds (#150900)
This flag applies to G_PTR_ADD instructions and indicates that the operation
implements an inbounds getelementptr operation, i.e., the pointer operand is in
bounds wrt. the allocated object it is based on, and the arithmetic does not
change that.
It is set when the IRTranslator lowers inbounds GEPs (currently only in some
cases, to be extended with a future PR), and in the
(build|materialize)ObjectPtrOffset functions.
Inbounds information is useful in ISel when we have instructions that perform
address computations whose intermediate steps must be in the same memory region
as the final result. A follow-up patch will start using it for AMDGPU's flat
memory instructions, where the immediate offset must not affect the memory
aperture of the address.
This is analogous to a concurrent effort in SDAG: #131862
(related: #140017, #141725).
For SWDEV-516125.
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 9aa8deb..27df7e3 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -211,7 +211,9 @@ MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, MachineInstrBuilder MachineIRBuilder::buildObjectPtrOffset(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) { - return buildPtrAdd(Res, Op0, Op1, MachineInstr::MIFlag::NoUWrap); + return buildPtrAdd(Res, Op0, Op1, + MachineInstr::MIFlag::NoUWrap | + MachineInstr::MIFlag::InBounds); } std::optional<MachineInstrBuilder> @@ -234,7 +236,8 @@ MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0, std::optional<MachineInstrBuilder> MachineIRBuilder::materializeObjectPtrOffset( Register &Res, Register Op0, const LLT ValueTy, uint64_t Value) { return materializePtrAdd(Res, Op0, ValueTy, Value, - MachineInstr::MIFlag::NoUWrap); + MachineInstr::MIFlag::NoUWrap | + MachineInstr::MIFlag::InBounds); } MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res, |