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author | Michael Maitland <michaeltmaitland@gmail.com> | 2024-09-17 10:08:39 -0400 |
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committer | GitHub <noreply@github.com> | 2024-09-17 10:08:39 -0400 |
commit | ee2add06836afdda6c86792441e6afdf6993f770 (patch) | |
tree | f5e0b1360da2205f0d473b4c5d662cb51dbb78b6 /llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | |
parent | 49a754a43d5592e08ef177db794126ddc676d6b5 (diff) | |
download | llvm-ee2add06836afdda6c86792441e6afdf6993f770.zip llvm-ee2add06836afdda6c86792441e6afdf6993f770.tar.gz llvm-ee2add06836afdda6c86792441e6afdf6993f770.tar.bz2 |
[GISEL] Fix bugs and clarify spec of G_EXTRACT_SUBVECTOR (#108848)
The implementation was missing the fact that `G_EXTRACT_SUBVECTOR`
destination and source vector can be different types.
Also fix a bug in the MIR builder for `G_EXTRACT_SUBVECTOR` to generate
the correct opcode.
Clarify the G_EXTRACT_SUBVECTOR specification.
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 925a1c7..59f2fc6 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -942,7 +942,7 @@ MachineInstrBuilder MachineIRBuilder::buildInsertSubvector(const DstOp &Res, MachineInstrBuilder MachineIRBuilder::buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Idx) { - return buildInstr(TargetOpcode::G_INSERT_SUBVECTOR, Res, + return buildInstr(TargetOpcode::G_EXTRACT_SUBVECTOR, Res, {Src, uint64_t(Idx)}); } |