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author | Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com> | 2023-07-31 12:14:34 +0530 |
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committer | Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com> | 2023-07-31 12:15:39 +0530 |
commit | d9847cde4841140a95404ea7b7d3a57f8bfbf976 (patch) | |
tree | baac74145467ab63363a95caf6560f2250040bdb /llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | |
parent | f2e44238ee35f9fb6aa6d07b07f3d6469a5e9416 (diff) | |
download | llvm-d9847cde4841140a95404ea7b7d3a57f8bfbf976.zip llvm-d9847cde4841140a95404ea7b7d3a57f8bfbf976.tar.gz llvm-d9847cde4841140a95404ea7b7d3a57f8bfbf976.tar.bz2 |
[GlobalISel] convergent intrinsics
Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:
- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
Out of the targets that currently have some support for GlobalISel, the patch
assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D154766
Diffstat (limited to 'llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 45 |
1 files changed, 35 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 962b54e..90358e7 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -775,30 +775,55 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res, return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)}); } -MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, - ArrayRef<Register> ResultRegs, - bool HasSideEffects) { - auto MIB = - buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS - : TargetOpcode::G_INTRINSIC); +static unsigned getIntrinsicOpcode(bool HasSideEffects, bool IsConvergent) { + if (HasSideEffects && IsConvergent) + return TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS; + if (HasSideEffects) + return TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS; + if (IsConvergent) + return TargetOpcode::G_INTRINSIC_CONVERGENT; + return TargetOpcode::G_INTRINSIC; +} + +MachineInstrBuilder +MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, + ArrayRef<Register> ResultRegs, + bool HasSideEffects, bool isConvergent) { + auto MIB = buildInstr(getIntrinsicOpcode(HasSideEffects, isConvergent)); for (unsigned ResultReg : ResultRegs) MIB.addDef(ResultReg); MIB.addIntrinsicID(ID); return MIB; } +MachineInstrBuilder +MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, + ArrayRef<Register> ResultRegs) { + auto Attrs = Intrinsic::getAttributes(getContext(), ID); + bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory(); + bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent); + return buildIntrinsic(ID, ResultRegs, HasSideEffects, isConvergent); +} + MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Results, - bool HasSideEffects) { - auto MIB = - buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS - : TargetOpcode::G_INTRINSIC); + bool HasSideEffects, + bool isConvergent) { + auto MIB = buildInstr(getIntrinsicOpcode(HasSideEffects, isConvergent)); for (DstOp Result : Results) Result.addDefToMIB(*getMRI(), MIB); MIB.addIntrinsicID(ID); return MIB; } +MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, + ArrayRef<DstOp> Results) { + auto Attrs = Intrinsic::getAttributes(getContext(), ID); + bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory(); + bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent); + return buildIntrinsic(ID, Results, HasSideEffects, isConvergent); +} + MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res, const SrcOp &Op) { return buildInstr(TargetOpcode::G_TRUNC, Res, Op); |