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| author | Craig Topper <craig.topper@intel.com> | 2020-01-07 11:09:33 -0800 |
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| committer | Craig Topper <craig.topper@intel.com> | 2020-01-07 11:22:04 -0800 |
| commit | afa8211e979c25100c2ed41d8da1e18b45d0ef2b (patch) | |
| tree | bfab69376fbbd6763e7257f8c2b72c6e4eeb46a6 /lldb/scripts/Python | |
| parent | b9376690a011765e35d9ca63abe0e7117985f1ed (diff) | |
| download | llvm-afa8211e979c25100c2ed41d8da1e18b45d0ef2b.zip llvm-afa8211e979c25100c2ed41d8da1e18b45d0ef2b.tar.gz llvm-afa8211e979c25100c2ed41d8da1e18b45d0ef2b.tar.bz2 | |
[X86] Improve lowering of (v2i64 (setgt X, -1)) on pre-SSE2 targets. Enable v2i64 in foldVectorXorShiftIntoCmp.
Similar to D72302 but for the canonical form for the opposite case. I've changed foldVectorXorShiftIntoCmp to form a target independent setcc node instead of PCMPGT now and enabled its for v2i64 on pre-SSE4.2 targets. The setcc should eventually get lowered to PCMPGT or the new v2i64 sequence.
Differential Revision: https://reviews.llvm.org/D72318
Diffstat (limited to 'lldb/scripts/Python')
0 files changed, 0 insertions, 0 deletions