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| author | Brox Chen <guochen2@amd.com> | 2025-09-02 21:26:44 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-02 21:26:44 -0400 |
| commit | bfe150cdfc58feb0499f129b4be653340f98e1fe (patch) | |
| tree | f96a213feadf8370e38f7163562025073ccb07b1 /clang/utils/TableGen/RISCVVEmitter.cpp | |
| parent | cb89ffdd34aa6b7e6d1417ef68e1d837c8e651a1 (diff) | |
| download | llvm-bfe150cdfc58feb0499f129b4be653340f98e1fe.zip llvm-bfe150cdfc58feb0499f129b4be653340f98e1fe.tar.gz llvm-bfe150cdfc58feb0499f129b4be653340f98e1fe.tar.bz2 | |
[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence (#154952)
update zext pattern with reg_sequence. This is a follow up from
https://github.com/llvm/llvm-project/pull/154211#discussion_r2288538817
Diffstat (limited to 'clang/utils/TableGen/RISCVVEmitter.cpp')
0 files changed, 0 insertions, 0 deletions