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| author | Brox Chen <guochen2@amd.com> | 2025-09-02 21:26:44 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-02 21:26:44 -0400 |
| commit | bfe150cdfc58feb0499f129b4be653340f98e1fe (patch) | |
| tree | f96a213feadf8370e38f7163562025073ccb07b1 | |
| parent | cb89ffdd34aa6b7e6d1417ef68e1d837c8e651a1 (diff) | |
| download | llvm-bfe150cdfc58feb0499f129b4be653340f98e1fe.zip llvm-bfe150cdfc58feb0499f129b4be653340f98e1fe.tar.gz llvm-bfe150cdfc58feb0499f129b4be653340f98e1fe.tar.bz2 | |
[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence (#154952)
update zext pattern with reg_sequence. This is a follow up from
https://github.com/llvm/llvm-project/pull/154211#discussion_r2288538817
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index fc46db9..46eab2a 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3106,9 +3106,7 @@ def : GCNPat< def : GCNPat< (i64 (DivergentUnaryFrag<zext> i16:$src)), - (REG_SEQUENCE VReg_64, - (INSERT_SUBREG (i32 (V_MOV_B32_e32 (i32 0))), VGPR_16:$src, lo16), sub0, - (S_MOV_B32 (i32 0)), sub1) + (REG_SEQUENCE VReg_64, $src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16, (V_MOV_B32_e32 (i32 0)), sub1) >; def : GCNPat< |