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| author | Lucas Prates <lucas.prates@arm.com> | 2020-11-12 10:54:28 +0000 |
|---|---|---|
| committer | Lucas Prates <lucas.prates@arm.com> | 2020-12-17 13:45:46 +0000 |
| commit | 97c006aabb6c831d68204bcb4aad8670af695618 (patch) | |
| tree | 00d87d8666f70787cba032ddb0e56bc188e6e3cb /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 42b92b31b8b8ee9fdcd68adfe57db11561a5edcd (diff) | |
| download | llvm-97c006aabb6c831d68204bcb4aad8670af695618.zip llvm-97c006aabb6c831d68204bcb4aad8670af695618.tar.gz llvm-97c006aabb6c831d68204bcb4aad8670af695618.tar.bz2 | |
[AArch64] Add a GPR64x8 register class
This adds a GPR64x8 register class that will be needed as the data
operand to the LD64B/ST64B family of instructions in the v8.7-A
Accelerator Extension, which load or store a contiguous range of eight
x-regs. It has to be its own register class so that register allocation
will have visibility of the full set of registers actually read/written
by the instructions, which will be needed when we add intrinsics and/or
inline asm access to this piece of architecture.
Patch written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91774
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
0 files changed, 0 insertions, 0 deletions