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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:27:40 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-17 17:28:10 +0300 |
| commit | 91373bf12ec66591addf56b9f447ec9befd6ddae (patch) | |
| tree | 5d36b3b2bd358aae8733420289d14f1eebfed1dc /clang/lib/CodeGen/CodeGenModule.cpp | |
| parent | 3274ce3a287dcd4d02b4d2c7a2bf60e942836e06 (diff) | |
| download | llvm-91373bf12ec66591addf56b9f447ec9befd6ddae.zip llvm-91373bf12ec66591addf56b9f447ec9befd6ddae.tar.gz llvm-91373bf12ec66591addf56b9f447ec9befd6ddae.tar.bz2 | |
[X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs
A few more tuples are being queried after D111546. Might be good to model them,
They all require a lot of manual assembly surgery.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/9bnKrefcG - for intels `Block RThroughput: =40.0`; for ryzens, `Block RThroughput: =16.0`
So could pick cost of `40`
For store we have:
https://godbolt.org/z/5s3s14dEY - for intels `Block RThroughput: =40.0`; for ryzens, `Block RThroughput: =16.0`
So we could pick cost of `40`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111945
Diffstat (limited to 'clang/lib/CodeGen/CodeGenModule.cpp')
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