[PATCH] [AArch64] Optional trapping exceptions support.

Trapping exceptions in AArch64 are optional.  The relevant exception
control bits in FPCR are are defined as RES0 hence the absence of
support can be detected by reading back the FPCR and comparing with
the desired value.

2 files changed, 23 insertions, 0 deletions

diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index d976999..07a4bbb 100644
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -35,5 +35,18 @@ feenableexcept (int excepts)
 
   _FPU_SETCW (fpcr);
 
+  /* Trapping exceptions are optional in AArch64 the relevant enable
+     bits in FPCR are RES0 hence the absence of support can be
+     detected by reading back the FPCR and comparing with the required
+     value.  */
+  if (excepts)
+    {
+      fpu_control_t updated_fpcr;
+
+      _FPU_GETCW (updated_fpcr);
+      if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
+	return -1;
+    }
+
   return original_excepts;
 }
diff --git a/sysdeps/aarch64/fpu/fesetenv.c b/sysdeps/aarch64/fpu/fesetenv.c
index 443c705..a2434e3 100644
--- a/sysdeps/aarch64/fpu/fesetenv.c
+++ b/sysdeps/aarch64/fpu/fesetenv.c
@@ -24,6 +24,7 @@ fesetenv (const fenv_t *envp)
 {
   fpu_control_t fpcr;
   fpu_fpsr_t fpsr;
+  fpu_control_t updated_fpcr;
 
   _FPU_GETCW (fpcr);
   _FPU_GETFPSR (fpsr);
@@ -51,6 +52,15 @@ fesetenv (const fenv_t *envp)
 
   _FPU_SETCW (fpcr);
 
+  /* Trapping exceptions are optional in AArch64 the relevant enable
+     bits in FPCR are RES0 hence the absence of support can be
+     detected by reading back the FPCR and comparing with the required
+     value.  */
+
+  _FPU_GETCW (updated_fpcr);
+  if ((updated_fpcr & fpcr) != fpcr)
+    return 1;
+
   return 0;
 }