aboutsummaryrefslogtreecommitdiff
path: root/sysdeps/aarch64/fpu
AgeCommit message (Expand)AuthorFilesLines
2025-01-13aarch64: Use 64-bit variable to access the special registersAdhemerval Zanella2-12/+27
2025-01-03AArch64: Improve codegen in SVE expm1f and usersLuna Lamb4-45/+44
2025-01-03AArch64: Add vector tanpi routinesJoe Ramsay12-1/+336
2025-01-03AArch64: Add vector cospi routinesJoe Ramsay12-0/+319
2025-01-03AArch64: Add vector sinpi to libmvecJoe Ramsay12-0/+309
2025-01-03AArch64: Improve codegen for SVE log1pf usersYat Long Poon5-122/+95
2025-01-03AArch64: Improve codegen for SVE logsYat Long Poon3-46/+113
2025-01-03AArch64: Improve codegen in SVE tansLuna Lamb2-41/+68
2025-01-03AArch64: Improve codegen in AdvSIMD asinhLuna Lamb1-55/+119
2025-01-01Update copyright dates with scripts/update-copyrightsPaul Eggert183-183/+183
2024-12-17AArch64: Improve codegen of AdvSIMD expf familyJoana Cruz5-118/+127
2024-12-17AArch64: Improve codegen of AdvSIMD atan(2)(f)Joana Cruz3-68/+160
2024-12-17AArch64: Improve codegen of AdvSIMD logf function familyJoana Cruz3-40/+66
2024-12-09AArch64: Improve codegen in users of ADVSIMD expm1 helperPierre Blanchard5-162/+135
2024-12-09AArch64: Improve codegen in users of ADVSIMD log1p helperPierre Blanchard4-127/+93
2024-12-09AArch64: Improve codegen in AdvSIMD logsPierre Blanchard3-106/+140
2024-12-09AArch64: Improve codegen in AdvSIMD powPierre Blanchard1-53/+62
2024-11-01AArch64: Remove SVE erf and erfc tablesJoe Ramsay16-2691/+50
2024-10-28AArch64: Small optimisation in AdvSIMD erf and erfcJoe Ramsay2-15/+23
2024-09-23AArch64: Simplify rounding-multiply pattern in several AdvSIMD routinesJoe Ramsay5-38/+30
2024-09-23AArch64: Improve codegen in users of ADVSIMD expm1f helperJoe Ramsay4-91/+58
2024-09-23AArch64: Improve codegen in users of AdvSIMD log1pf helperJoe Ramsay5-139/+146
2024-09-23AArch64: Improve codegen in SVE F32 logsJoe Ramsay3-47/+69
2024-09-23AArch64: Improve codegen in SVE expf & related routinesJoe Ramsay5-148/+136
2024-09-19AArch64: Add vector logp1 alias for log1pJoe Ramsay7-0/+25
2024-09-09aarch64: Avoid redundant MOVs in AdvSIMD F32 logsJoe Ramsay3-45/+72
2024-05-21aarch64/fpu: Add vector variants of powJoe Ramsay19-12/+2223
2024-05-16aarch64/fpu: Add vector variants of cbrtJoe Ramsay12-0/+513
2024-05-16aarch64/fpu: Add vector variants of hypotJoe Ramsay12-0/+316
2024-05-14aarch64: Fix AdvSIMD libmvec routines for big-endianJoe Ramsay17-85/+119
2024-04-04aarch64/fpu: Add vector variants of erfcJoe Ramsay15-1/+4884
2024-04-04aarch64/fpu: Add vector variants of tanhJoe Ramsay12-1/+366
2024-04-04aarch64/fpu: Add vector variants of sinhJoe Ramsay14-0/+559
2024-04-04aarch64/fpu: Add vector variants of atanhJoe Ramsay12-0/+275
2024-04-04aarch64/fpu: Add vector variants of asinhJoe Ramsay12-0/+476
2024-04-04aarch64/fpu: Add vector variants of acoshJoe Ramsay17-0/+640
2024-04-04aarch64/fpu: Add vector variants of coshJoe Ramsay16-1/+635
2024-04-04aarch64/fpu: Add vector variants of erfJoe Ramsay17-1/+4518
2024-02-26aarch64/fpu: Sync libmvec routines from 2.39 and before with AORJoe Ramsay18-105/+111
2024-01-01Update copyright dates with scripts/update-copyrightsPaul Eggert121-121/+121
2023-12-20aarch64: Add SIMD attributes to math functions with vector versionsJoe Ramsay2-0/+113
2023-12-20aarch64: Add half-width versions of AdvSIMD f32 libmvec routinesJoe Ramsay18-14/+108
2023-11-29aarch64: Improve special-case handling in AdvSIMD double-precision libmvec ro...Joe Ramsay1-1/+7
2023-11-22aarch64: Fix libmvec benchmarksJoe Ramsay2-49/+81
2023-11-20aarch64: Add vector implementations of expm1 routinesJoe Ramsay11-0/+450
2023-11-10aarch64: Add vector implementations of log1p routinesJoe Ramsay11-0/+488
2023-11-10aarch64: Add vector implementations of atan2 routinesJoe Ramsay13-0/+523
2023-11-10aarch64: Add vector implementations of atan routinesJoe Ramsay11-0/+395
2023-11-10aarch64: Add vector implementations of acos routinesJoe Ramsay11-1/+428
2023-11-10aarch64: Add vector implementations of asin routinesJoe Ramsay11-1/+395
generated by cgit v1.1 at 2025-02-04 23:34:03 +0000