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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-06-28 12:19:38 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-06-30 09:04:22 +0100 |
| commit | 78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9 (patch) | |
| tree | 989c1b12f52fc1886b0b493aa8cc0e01e6fc1d1f /sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | |
| parent | 3bb1af20513b8b70b8d404c71fb0956f00f8bf6b (diff) | |
| download | glibc-78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9.zip glibc-78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9.tar.gz glibc-78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9.tar.bz2 | |
aarch64: Add vector implementations of log routines
Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines. Log lookup table
added as HIDDEN symbol to allow it to be shared between AdvSIMD and
SVE variants.
As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c')
| -rw-r--r-- | sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c index 50e776b..c240738 100644 --- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c @@ -24,4 +24,5 @@ #define VEC_TYPE float32x4_t VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf) +VPCS_VECTOR_WRAPPER (logf_advsimd, _ZGVnN4v_logf) VPCS_VECTOR_WRAPPER (sinf_advsimd, _ZGVnN4v_sinf) |