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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-06-28 12:19:37 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-06-30 09:04:16 +0100 |
| commit | 3bb1af20513b8b70b8d404c71fb0956f00f8bf6b (patch) | |
| tree | 1043f476abc9d2587a2d2ee8f1dabd06b104162a /sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | |
| parent | aed39a3aa3ea68b14dce3395fb14b1416541e6c6 (diff) | |
| download | glibc-3bb1af20513b8b70b8d404c71fb0956f00f8bf6b.zip glibc-3bb1af20513b8b70b8d404c71fb0956f00f8bf6b.tar.gz glibc-3bb1af20513b8b70b8d404c71fb0956f00f8bf6b.tar.bz2 | |
aarch64: Add vector implementations of sin routines
Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines.
As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c')
| -rw-r--r-- | sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c index fa14686..50e776b 100644 --- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c @@ -24,3 +24,4 @@ #define VEC_TYPE float32x4_t VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf) +VPCS_VECTOR_WRAPPER (sinf_advsimd, _ZGVnN4v_sinf) |