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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-06-28 12:19:39 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-06-30 09:04:26 +0100 |
| commit | 4a9392ffc27ad280f84779eea3ba01f2c134d1d8 (patch) | |
| tree | 8716efd89aadc70338eeff9622cfcbdd7ff7911e /sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | |
| parent | 78c01a5cbeb6717ffa2d4d66bb90ac5c39bd81a9 (diff) | |
| download | glibc-4a9392ffc27ad280f84779eea3ba01f2c134d1d8.zip glibc-4a9392ffc27ad280f84779eea3ba01f2c134d1d8.tar.gz glibc-4a9392ffc27ad280f84779eea3ba01f2c134d1d8.tar.bz2 | |
aarch64: Add vector implementations of exp routines
Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines.
As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c')
| -rw-r--r-- | sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c index c240738..d4a9ac7 100644 --- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c @@ -24,5 +24,6 @@ #define VEC_TYPE float32x4_t VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf) +VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf) VPCS_VECTOR_WRAPPER (logf_advsimd, _ZGVnN4v_logf) VPCS_VECTOR_WRAPPER (sinf_advsimd, _ZGVnN4v_sinf) |