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AgeCommit message (Expand)AuthorFilesLines
2017-04-22Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson2-188/+113
2017-04-08Add support for fcvtl and fcvtl2.Jim Wilson2-0/+51
2017-04-08Support the fcmXX zero instructions.Jim Wilson2-0/+151
2017-03-25Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2-1/+6
2017-03-03Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson2-4/+21
2017-02-25Add missing smov support, and clean up existing umov support.Jim Wilson2-75/+134
2017-02-25Add missing cnt (popcount) instruction support.Jim Wilson2-0/+57
2017-02-19Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson2-17/+31
2017-02-14Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson2-49/+18
2017-02-14Fix bit/bif instructions.Jim Wilson2-10/+14
2017-02-14Add ldn/stn single support, fix ldnr support.Jim Wilson2-269/+294
2017-01-23Add support for cmtst.Jim Wilson2-0/+5
2017-01-17Fixes for addv and xtn2 instructions.Jim Wilson2-31/+24
2017-01-09Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson2-17/+55
2017-01-04Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson3-33/+71
2017-01-01update copyright year range in GDB filesJoel Brobecker11-11/+11
2016-12-21Fix bugs with float compare and Inf operands.Jim Wilson2-0/+34
2016-12-13Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson2-36/+21
2016-12-03Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2-3/+8
2016-12-01Fix typo in ChangeLog entry.Jim Wilson1-1/+1
2016-12-01Fix bug with FP stur instructions.Jim Wilson2-6/+11
2016-08-15sim: unify symbol table handlingMike Frysinger6-38/+38
2016-08-12Undo the previous change to the aarch64 sim - exporting aarch64_step() - and ...Nick Clifton3-9/+19
2016-08-11Export the single step function from the AArch64 simulator.Nick Clifton4-9/+19
2016-07-27Wean gdb and sim off private libbfd.h headerAlan Modra2-1/+4
2016-07-21Fix typo fsqrt -> sqrtf.Nick Clifton1-1/+1
2016-07-21Use fsqrt() to calculate float (rather than double) square root.Nick Clifton2-1/+5
2016-06-30Add support for simulating big-endian AArch64 binaries.Jim Wilson3-9/+30
2016-05-06Add support for FMLA (by element) to AArch64 sim.Nick Clifton2-2/+77
2016-04-27Add support for the --trace-decode option to the AArch64 simulator.Nick Clifton2-7/+317
2016-04-04Ignore DWARF debug information with a version of 0 - assume that it is padding.Nick Clifton1-12/+189
2016-03-30Fix more bugs in AArch64 simulator.Nick Clifton5-196/+323
2016-03-29Tidy up AArch64 simulator code.Nick Clifton4-1469/+1413
2016-03-23More AArch64 simulator improvements.Nick Clifton6-278/+721
2016-03-18Fix thinko in new GET_VEC_ELEMENT macro.Nick Clifton2-1/+2
2016-03-18Fix code to check for illegal element numbers when accessing AArch64 vector r...Nick Clifton2-2/+6
2016-03-18Add simulation of MUL and NEG instructions to AArch64 simulator.Nick Clifton5-223/+341
2016-03-03Fix bugs in the simulation of the AArch64's ADDP, FADDP, LD1, CCMP and CCMP i...Nick Clifton2-44/+93
2016-01-10sim: move many common settings from CPPFLAGS to config.hMike Frysinger3-68/+124
2016-01-10sim: drop unused SIM_AC_OPTION_PACKAGESMike Frysinger2-7/+6
2016-01-10sim: allow the environment configure option everywhereMike Frysinger3-23/+27
2016-01-10sim: allow the assert configure option everywhereMike Frysinger2-2/+23
2016-01-10sim: drop targ-vals.def->nltvals.def indirectionMike Frysinger2-57/+5
2016-01-10sim: allow the inline configure option everywhereMike Frysinger3-51/+41
2016-01-10sim: drop --enable-sim-{regparm,stdcall} optionsMike Frysinger2-12/+6
2016-01-10sim: drop --enable-sim-cflags optionMike Frysinger2-23/+6
2016-01-09sim: drop common/cconfig.h in favor of a single config.hMike Frysinger3-3/+406
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger2-2/+8
2016-01-05sim: aarch64: switch to common disassembler tracingMike Frysinger5-137/+30
2016-01-04sim: unify min/max macrosMike Frysinger2-17/+20
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