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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-02-19 13:16:56 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-02-19 13:16:56 -0800 |
| commit | 2e7e5e28909bcffe2267b417f9cff0441b576fba (patch) | |
| tree | c2aac362b90239464de9622e1cbdecc7e58851f1 /sim/aarch64 | |
| parent | ceae703d41819c1f03e3250b6e6df64dc6e7d3ff (diff) | |
| download | gdb-2e7e5e28909bcffe2267b417f9cff0441b576fba.zip gdb-2e7e5e28909bcffe2267b417f9cff0441b576fba.tar.gz gdb-2e7e5e28909bcffe2267b417f9cff0441b576fba.tar.bz2 | |
Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.
sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.
sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.
Diffstat (limited to 'sim/aarch64')
| -rw-r--r-- | sim/aarch64/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/aarch64/simulator.c | 42 |
2 files changed, 31 insertions, 17 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index e8d66a6..dbe68ec 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,9 @@ +2017-02-19 Jim Wilson <jim.wilson@linaro.org> + + * simulator.c (do_vec_ADDV): Mov val declaration inside each case, + with type set to input type size. + (do_vec_xtl): Change bias from 3 to 4 for byte case. + 2017-02-14 Jim Wilson <jim.wilson@linaro.org> * simulator.c (do_vec_MLA): Rewrite switch body. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 7c28219..d31cb10 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -3433,7 +3433,6 @@ do_vec_ADDV (sim_cpu *cpu) unsigned vm = INSTR (9, 5); unsigned rd = INSTR (4, 0); unsigned i; - uint64_t val = 0; int full = INSTR (30, 30); NYI_assert (29, 24, 0x0E); @@ -3443,24 +3442,33 @@ do_vec_ADDV (sim_cpu *cpu) switch (INSTR (23, 22)) { case 0: - for (i = 0; i < (full ? 16 : 8); i++) - val += aarch64_get_vec_u8 (cpu, vm, i); - aarch64_set_vec_u64 (cpu, rd, 0, val); - return; + { + uint8_t val = 0; + for (i = 0; i < (full ? 16 : 8); i++) + val += aarch64_get_vec_u8 (cpu, vm, i); + aarch64_set_vec_u64 (cpu, rd, 0, val); + return; + } case 1: - for (i = 0; i < (full ? 8 : 4); i++) - val += aarch64_get_vec_u16 (cpu, vm, i); - aarch64_set_vec_u64 (cpu, rd, 0, val); - return; + { + uint16_t val = 0; + for (i = 0; i < (full ? 8 : 4); i++) + val += aarch64_get_vec_u16 (cpu, vm, i); + aarch64_set_vec_u64 (cpu, rd, 0, val); + return; + } case 2: - if (! full) - HALT_UNALLOC; - for (i = 0; i < 4; i++) - val += aarch64_get_vec_u32 (cpu, vm, i); - aarch64_set_vec_u64 (cpu, rd, 0, val); - return; + { + uint32_t val = 0; + if (! full) + HALT_UNALLOC; + for (i = 0; i < 4; i++) + val += aarch64_get_vec_u32 (cpu, vm, i); + aarch64_set_vec_u64 (cpu, rd, 0, val); + return; + } case 3: HALT_UNALLOC; @@ -5694,7 +5702,7 @@ do_vec_xtl (sim_cpu *cpu) NYI_assert (19, 19, 1); shift = INSTR (18, 16); - bias *= 3; + bias *= 4; for (i = 0; i < 8; i++) v[i] = aarch64_get_vec_s8 (cpu, vs, i + bias) << shift; for (i = 0; i < 8; i++) @@ -5730,7 +5738,7 @@ do_vec_xtl (sim_cpu *cpu) NYI_assert (19, 19, 1); shift = INSTR (18, 16); - bias *= 3; + bias *= 4; for (i = 0; i < 8; i++) v[i] = aarch64_get_vec_u8 (cpu, vs, i + bias) << shift; for (i = 0; i < 8; i++) |