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2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas6-2448/+2496
2024-06-11MIPS/opcodes: Add MIPS Allegrex DBREAK instructionDavid Guillen Fandos1-1/+1
2024-06-11MIPS/opcodes: Exclude trap instructions for MIPS AllegrexDavid Guillen Fandos1-30/+30
2024-06-10Revert "MIPS/Allegrex: Exclude trap instructions"Maciej W. Rozycki1-30/+30
2024-06-10Revert "MIPS/Allegrex: Enable dbreak instruction"Maciej W. Rozycki1-1/+1
2024-06-10MIPS/Allegrex: Enable dbreak instructionDavid Guillen Fandos1-1/+1
2024-06-10MIPS/Allegrex: Exclude trap instructionsDavid Guillen Fandos1-30/+30
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich4-4223/+4223
2024-06-10x86: disassembler macro for condition codeJan Beulich3-281/+71
2024-06-10x86/APX: support extended SETcc formJan Beulich2-312/+555
2024-06-10x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insnsJan Beulich2-15/+15
2024-06-10autoupdate: regen after replacing obsolete macrosMatthieu Longo1-4/+2
2024-06-10autoupdate: add square brackets around arguments of AC_INITMatthieu Longo1-1/+1
2024-06-10autoupdate: replace obsolete macros AC_AIX, AC_MINIX, and AC_GNU_SOURCEMatthieu Longo1-1/+0
2024-06-06opcodes/riscv: prevent future use of disassemble_info::fprintf_funcAndrew Burgess1-0/+5
2024-06-06opcodes/riscv: add styling support to print_reg_listAndrew Burgess1-14/+37
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng1-0/+4
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng1-0/+4
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng1-0/+5
2024-06-05arm: remove disassembly support for the FPA co-processorRichard Earnshaw1-196/+1
2024-06-05Fix illegal memory access when bfd_get_section_contents is called with a NULL...Nick Clifton1-0/+7
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett1-0/+26
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett2-0/+8
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+3
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich4-5657/+5662
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com6-130/+252
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com10-362/+509
2024-05-28opcodes: add a .gitattributes file for aarch64 autogenerated file exceptionsRichard Earnshaw1-0/+3
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich2-16/+16
2024-05-22aarch64: fix incorrect encoding for system register pmsdsfr_el1Matthieu Longo1-1/+1
2024-05-22Support APX zero-upperCui, Lili8-6243/+6985
2024-05-21aarch64: Fix the hyphenated disassembly comment.Srinath Parvathaneni1-2/+2
2024-05-20aarch64: Add support for the fpmr system registerClaudio Bantaloukas1-0/+1
2024-05-17aarch64: correct SVE2.1 ld2q (scalar plus scalar)Jan Beulich2-12/+21
2024-05-17aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate)Jan Beulich1-4/+4
2024-05-16aarch64: fp8 convert and scale - add sme2 insn variantsVictor Do Nascimento2-136/+328
2024-05-16aarch64: fp8 convert and scale - add sve2 insn variantsVictor Do Nascimento2-31/+183
2024-05-16aarch64: fp8 convert and scale - Add advsimd insn variantsVictor Do Nascimento2-36/+220
2024-05-16aarch64: fp8 convert and scale - add feature flags and related structuresVictor Do Nascimento1-0/+18
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo1-0/+4
2024-05-15RISC-V: Search for mapping symbols from the last one foundJoseph Faulls1-8/+4
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw1-178/+1
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu1-88/+88
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili2-115/+117
2024-05-06x86: Drop SwapSourcesCui, Lili3-319/+319
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili3-655/+657
2024-05-03x86: tidy <sse*> templatesJan Beulich1-20/+20
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich2-230/+261
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich2-653/+1987
2024-05-03x86: zap value-less Disp8MemShift from non-EVEX templatesJan Beulich1-7/+19