| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-06-14 | aarch64: add SPMU system registers missed in f01ae0392ed | Matthieu Longo | 1 | -0/+79 |
| 2024-06-12 | aarch64: add Branch Record Buffer extension instructions | Claudio Bantaloukas | 6 | -2448/+2496 |
| 2024-06-11 | MIPS/opcodes: Add MIPS Allegrex DBREAK instruction | David Guillen Fandos | 1 | -1/+1 |
| 2024-06-11 | MIPS/opcodes: Exclude trap instructions for MIPS Allegrex | David Guillen Fandos | 1 | -30/+30 |
| 2024-06-10 | Revert "MIPS/Allegrex: Exclude trap instructions" | Maciej W. Rozycki | 1 | -30/+30 |
| 2024-06-10 | Revert "MIPS/Allegrex: Enable dbreak instruction" | Maciej W. Rozycki | 1 | -1/+1 |
| 2024-06-10 | MIPS/Allegrex: Enable dbreak instruction | David Guillen Fandos | 1 | -1/+1 |
| 2024-06-10 | MIPS/Allegrex: Exclude trap instructions | David Guillen Fandos | 1 | -30/+30 |
| 2024-06-10 | x86/APX: convert ZU to operand constraint | Jan Beulich | 4 | -4223/+4223 |
| 2024-06-10 | x86: disassembler macro for condition code | Jan Beulich | 3 | -281/+71 |
| 2024-06-10 | x86/APX: support extended SETcc form | Jan Beulich | 2 | -312/+555 |
| 2024-06-10 | x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insns | Jan Beulich | 2 | -15/+15 |
| 2024-06-10 | autoupdate: regen after replacing obsolete macros | Matthieu Longo | 1 | -4/+2 |
| 2024-06-10 | autoupdate: add square brackets around arguments of AC_INIT | Matthieu Longo | 1 | -1/+1 |
| 2024-06-10 | autoupdate: replace obsolete macros AC_AIX, AC_MINIX, and AC_GNU_SOURCE | Matthieu Longo | 1 | -1/+0 |
| 2024-06-06 | opcodes/riscv: prevent future use of disassemble_info::fprintf_func | Andrew Burgess | 1 | -0/+5 |
| 2024-06-06 | opcodes/riscv: add styling support to print_reg_list | Andrew Burgess | 1 | -14/+37 |
| 2024-06-06 | RISC-V: Add support for Zvfbfwma extension | Xiao Zeng | 1 | -0/+4 |
| 2024-06-06 | RISC-V: Add support for Zvfbfmin extension | Xiao Zeng | 1 | -0/+4 |
| 2024-06-06 | RISC-V: Add support for Zfbfmin extension | Xiao Zeng | 1 | -0/+5 |
| 2024-06-05 | arm: remove disassembly support for the FPA co-processor | Richard Earnshaw | 1 | -196/+1 |
| 2024-06-05 | Fix illegal memory access when bfd_get_section_contents is called with a NULL... | Nick Clifton | 1 | -0/+7 |
| 2024-06-05 | RISC-V: Add support for XCVmem extension in CV32E40P | Mary Bennett | 1 | -0/+26 |
| 2024-06-05 | RISC-V: Add support for XCVbi extension in CV32E40P | Mary Bennett | 2 | -0/+8 |
| 2024-06-05 | RISC-V: Add support for XCVelw extension in CV32E40P | Mary Bennett | 1 | -0/+3 |
| 2024-05-29 | x86/Intel: warn about undue mnemonic suffixes | Jan Beulich | 4 | -5657/+5662 |
| 2024-05-28 | gas, aarch64: Add SVE2 lut extension | saurabh.jha@arm.com | 6 | -130/+252 |
| 2024-05-28 | gas, aarch64: Add AdvSIMD lut extension | saurabh.jha@arm.com | 10 | -362/+509 |
| 2024-05-28 | opcodes: add a .gitattributes file for aarch64 autogenerated file exceptions | Richard Earnshaw | 1 | -0/+3 |
| 2024-05-24 | x86: correct VCVT{,U}SI2SD | Jan Beulich | 2 | -16/+16 |
| 2024-05-22 | aarch64: fix incorrect encoding for system register pmsdsfr_el1 | Matthieu Longo | 1 | -1/+1 |
| 2024-05-22 | Support APX zero-upper | Cui, Lili | 8 | -6243/+6985 |
| 2024-05-21 | aarch64: Fix the hyphenated disassembly comment. | Srinath Parvathaneni | 1 | -2/+2 |
| 2024-05-20 | aarch64: Add support for the fpmr system register | Claudio Bantaloukas | 1 | -0/+1 |
| 2024-05-17 | aarch64: correct SVE2.1 ld2q (scalar plus scalar) | Jan Beulich | 2 | -12/+21 |
| 2024-05-17 | aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate) | Jan Beulich | 1 | -4/+4 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sme2 insn variants | Victor Do Nascimento | 2 | -136/+328 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sve2 insn variants | Victor Do Nascimento | 2 | -31/+183 |
| 2024-05-16 | aarch64: fp8 convert and scale - Add advsimd insn variants | Victor Do Nascimento | 2 | -36/+220 |
| 2024-05-16 | aarch64: fp8 convert and scale - add feature flags and related structures | Victor Do Nascimento | 1 | -0/+18 |
| 2024-05-16 | aarch64: add SPMU feature and its associated registers | Matthieu Longo | 1 | -0/+4 |
| 2024-05-15 | RISC-V: Search for mapping symbols from the last one found | Joseph Faulls | 1 | -8/+4 |
| 2024-05-14 | arm: opcodes: remove Maverick disassembly. | Richard Earnshaw | 1 | -178/+1 |
| 2024-05-08 | RISC-V: Support B, Zaamo and Zalrsc extensions. | Nelson Chu | 1 | -88/+88 |
| 2024-05-06 | x86: Drop using extension_opcode to encode vvvv register | Cui, Lili | 2 | -115/+117 |
| 2024-05-06 | x86: Drop SwapSources | Cui, Lili | 3 | -319/+319 |
| 2024-05-06 | x86: Use vexvvvv as the switch state to encode the vvvv register | Cui, Lili | 3 | -655/+657 |
| 2024-05-03 | x86: tidy <sse*> templates | Jan Beulich | 1 | -20/+20 |
| 2024-05-03 | x86/APX: further extend SSE2AVX coverage | Jan Beulich | 2 | -230/+261 |
| 2024-05-03 | x86/APX: extend SSE2AVX coverage | Jan Beulich | 2 | -653/+1987 |
