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path: root/opcodes/mips-opc.c
AgeCommit message (Expand)AuthorFilesLines
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-06-15Add additional missing Allegrex CPU instructionsDavid Guillen Fandos1-14/+24
2023-06-15Add rotation instructions to MIPS Allegrex CPUDavid Guillen Fandos1-7/+7
2023-06-15Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos1-26/+29
2023-06-15Revert "MIPS: sync oprand char usage between mips and micromips"Maciej W. Rozycki1-18/+10
2023-06-05MIPS: sync oprand char usage between mips and micromipsYunQiang Su1-10/+18
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-03-06MIPS/opcodes: Fix alias annotation for branch instructionsMaciej W. Rozycki1-5/+6
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki1-66/+68
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki1-51/+51
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki1-4/+0
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki1-2/+3
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki1-12/+14
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki1-4/+3
2021-03-31Use bool in opcodesAlan Modra1-22/+22
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-05-21MIPS/gas: Reject $0 as source register for DAUI instructionFaraz Shahbazker1-1/+1
2019-05-10Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6Faraz Shahbazker1-4/+4
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker1-0/+5
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett1-0/+8
2019-04-09[MIPS] Add RDHWR with the SEL field for MIPS R6.Robert Suchanek1-0/+1
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu1-1/+1
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu1-0/+7
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu1-64/+66
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu1-4/+7
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu1-80/+83
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-0/+8
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+14
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong1-1/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-06-30MIPS/opcodes: Reorder LSA and DLSA instructionsMaciej W. Rozycki1-3/+3
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki1-8/+9
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-0/+11
2017-05-12MIPS/opcodes: Mark descriptive SYNC mnemonics as aliasesMaciej W. Rozycki1-9/+9
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-07-13MIPS/opcodes: Address issues with NAL disassemblyMaciej W. Rozycki1-1/+1
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune1-0/+2
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-11-09Move copy_u.w to MSA64 ASE, remove copy_u.d.Robert Suchanek1-2/+1
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis1-1/+1
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-4/+4
2015-08-10Add SIGRIE instruction for MIPS R6Robert Suchanek1-0/+1
2015-03-13MIPS: Fix constraint issues with the R6 beqc and bnec instructionsAndrew Bennett1-2/+2
2015-03-13Add support for MIPS R6 evp and dvp instructions.Andrew Bennett1-0/+4
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-12-16Add in a JALRC alias and fix the NAL instruction.Matthew Fortune1-1/+2
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S1-3/+10
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