| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-07-18 | opcodes: aarch64: denote subclasses for insns of iclass dp_2src | Indu Bhagat | 1 | -24/+24 |
| 2024-07-18 | opcodes: aarch64: add flags to denote subclasses of uncond branches | Indu Bhagat | 1 | -19/+19 |
| 2024-07-18 | opcodes: aarch64: add flags to denote subclasses of arithmetic insns | Indu Bhagat | 1 | -15/+15 |
| 2024-07-18 | opcodes: aarch64: add flags to denote subclasses of ldst insns | Indu Bhagat | 1 | -43/+43 |
| 2024-07-12 | aarch64: Add support for sme2.1 zero instructions. | Srinath Parvathaneni | 1 | -0/+18 |
| 2024-07-12 | aarch64: Add support for sme2.1 movaz instructions. | Srinath Parvathaneni | 1 | -0/+19 |
| 2024-07-12 | aarch64: Add support for sme2.1 luti2 and luti4 instructions. | Srinath Parvathaneni | 1 | -0/+10 |
| 2024-07-08 | aarch64: Add support for sve2p1 pmov instruction. | srinath | 1 | -3/+51 |
| 2024-07-08 | aarch64: Add support for sve2p1 tbxq instruction. | Srinath Parvathaneni | 1 | -0/+1 |
| 2024-07-08 | aarch64: Add support for sve2p1 zipq[1-2] instructions. | Srinath Parvathaneni | 1 | -0/+2 |
| 2024-07-08 | aarch64: Add support for sve2p1 uzpq[1-2] instructions. | Srinath Parvathaneni | 1 | -0/+2 |
| 2024-07-08 | aarch64: Add support for sve2p1 tblq instruction. | Srinath Parvathaneni | 1 | -0/+1 |
| 2024-07-08 | aarch64: Add support for sve2p1 orqv instruction. | Srinath Parvathaneni | 1 | -0/+1 |
| 2024-06-26 | aarch64: FP8 scale and convert - Implement minor improvements | Victor Do Nascimento | 1 | -12/+12 |
| 2024-06-25 | aarch64: Fix FEAT_B16B16 sve2 instruction constraints. | Srinath Parvathaneni | 1 | -23/+23 |
| 2024-06-25 | arch64: Fix the wrong constraint used for sve2p1 instructions. | Srinath Parvathaneni | 1 | -13/+12 |
| 2024-06-25 | aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands. | Srinath Parvathaneni | 1 | -26/+22 |
| 2024-06-25 | aarch64: Fix sve2p1 extq instruction operands. | Srinath Parvathaneni | 1 | -4/+3 |
| 2024-06-25 | aarch64: Fix sve2p1 dupq instruction operands. | Srinath Parvathaneni | 1 | -5/+6 |
| 2024-06-24 | aarch64: Add SME FP8 multiplication instructions | Andrew Carlotti | 1 | -0/+74 |
| 2024-06-24 | aarch64: Add FP8 Neon and SVE multiplication instructions | Andrew Carlotti | 1 | -0/+112 |
| 2024-06-24 | gas, aarch64: Add SME2 lutv2 extension | saurabh.jha@arm.com | 1 | -0/+33 |
| 2024-06-12 | aarch64: add Branch Record Buffer extension instructions | Claudio Bantaloukas | 1 | -0/+15 |
| 2024-05-28 | gas, aarch64: Add SVE2 lut extension | saurabh.jha@arm.com | 1 | -1/+35 |
| 2024-05-28 | gas, aarch64: Add AdvSIMD lut extension | saurabh.jha@arm.com | 1 | -1/+37 |
| 2024-05-17 | aarch64: correct SVE2.1 ld2q (scalar plus scalar) | Jan Beulich | 1 | -1/+1 |
| 2024-05-17 | aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate) | Jan Beulich | 1 | -4/+4 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sme2 insn variants | Victor Do Nascimento | 1 | -0/+16 |
| 2024-05-16 | aarch64: fp8 convert and scale - add sve2 insn variants | Victor Do Nascimento | 1 | -0/+20 |
| 2024-05-16 | aarch64: fp8 convert and scale - Add advsimd insn variants | Victor Do Nascimento | 1 | -0/+41 |
| 2024-05-16 | aarch64: fp8 convert and scale - add feature flags and related structures | Victor Do Nascimento | 1 | -0/+18 |
| 2024-04-03 | Arm64: check tied operand specifier in aarch64-gen | Jan Beulich | 1 | -1/+1 |
| 2024-03-19 | gas, aarch64: Add faminmax extension | Saurabh Jha | 1 | -0/+30 |
| 2024-03-18 | aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT instructions | Yury Khrustalev | 1 | -0/+18 |
| 2024-03-18 | aarch64: Add support for (M)ADDPT and (M)SUBPT instructions | Yury Khrustalev | 1 | -1/+19 |
| 2024-03-18 | Arm64: check matching operands for predicated B16B16 insns | Jan Beulich | 1 | -7/+7 |
| 2024-03-18 | Arm64: correct B16B16 indexed bf{mla,mls,mul} | Jan Beulich | 1 | -3/+3 |
| 2024-02-29 | aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions. | Srinath Parvathaneni | 1 | -2/+2 |
| 2024-02-27 | aarch64: rename internals related to PAuth feature to use pauth in their nami... | Matthieu Longo | 1 | -38/+38 |
| 2024-01-26 | aarch64: move SHA512 instructions to +sha3 | Andrew Carlotti | 1 | -5/+5 |
| 2024-01-15 | aarch64: rcpc3: Add FP load/store insns | Victor Do Nascimento | 1 | -0/+4 |
| 2024-01-15 | aarch64: rcpc3: Add integer load/store insns | Victor Do Nascimento | 1 | -0/+5 |
| 2024-01-15 | aarch64: rcpc3: Define RCPC3_INSN macro | Victor Do Nascimento | 1 | -0/+2 |
| 2024-01-15 | aarch64: rcpc3: New RCPC3_ADDR operand types | Victor Do Nascimento | 1 | -1/+15 |
| 2024-01-15 | aarch64: rcpc3: Add +rcpc3 architectural feature support flag | Victor Do Nascimento | 1 | -0/+4 |
| 2024-01-15 | aarch64: Add SVE2.1 Contiguous load/store instructions. | Srinath Parvathaneni | 1 | -1/+33 |
| 2024-01-15 | PATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax instructions. | Srinath Parvathaneni | 1 | -0/+12 |
| 2024-01-15 | aarch64: Add SVE2.1 dupq, eorqv and extq instructions. | Srinath Parvathaneni | 1 | -0/+10 |
| 2024-01-15 | aarch64: Add support for FEAT_SVE2p1. | Srinath Parvathaneni | 1 | -0/+29 |
| 2024-01-15 | aarch64: Add support for FEAT_SME2p1 instructions. | Srinath Parvathaneni | 1 | -0/+36 |
