aboutsummaryrefslogtreecommitdiff
path: root/opcodes/ChangeLog
AgeCommit message (Expand)AuthorFilesLines
2016-11-11[AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy1-0/+7
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-0/+9
2016-11-11[AArch64] Increase max_num_aliases in aarch64-genSzabolcs Nagy1-0/+4
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-0/+14
2016-11-09Update opcodes/ChangeLogH.J. Lu1-0/+1
2016-11-09X86: Merge AVX512F vmovqH.J. Lu1-0/+4
2016-11-08X86: Remove the THREE_BYTE_0F7A entryH.J. Lu1-0/+7
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu1-0/+14
2016-11-04arc/nps400: Validate address type operands correctlyAndrew Burgess1-0/+6
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall1-0/+11
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess1-0/+30
2016-11-03arc: Swap highbyte and lowbyte in print_insn_arcGraham Markall1-0/+4
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall1-0/+7
2016-11-03arc/opcodes/nps400: Fix some instruction masksAndrew Burgess1-0/+4
2016-11-03X86: Reuse opcode 0x80 decoder for opcode 0x82H.J. Lu1-0/+19
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu1-0/+18
2016-11-03X86: Rename REG_82 to REG_83H.J. Lu1-0/+7
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+13
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+17
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+11
2016-10-21X86: Remove pcommit instructionH.J. Lu1-0/+13
2016-10-20Check invalid mask registersH.J. Lu1-0/+9
2016-10-18Check addr32flag instead of sizeflag for rip/eipH.J. Lu1-0/+6
2016-10-18Remove the remaining SSE5 supportH.J. Lu1-0/+5
2016-10-18AArch64/opcodes: Correct an `index' global shadowing errorMaciej W. Rozycki1-0/+5
2016-10-17Removed pseudo invalid instructions opcodes.Cupertino Miranda1-0/+4
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu1-0/+5
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang1-0/+5
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang1-0/+6
2016-10-07bfd_merge_private_bfd_data tidyAlan Modra1-0/+4
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+17
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra1-0/+6
2016-10-06Don't use boolean OR in arithmetic expressionsAlan Modra1-0/+5
2016-09-30Don't assign alt twiceH.J. Lu1-0/+5
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang1-0/+5
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra1-0/+16
2016-09-26When building target binaries, ensure that the warning flags selected for the...Vlad Zakharov1-0/+5
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu1-0/+14
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford1-0/+6
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford1-0/+5
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-0/+10
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+35
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+23
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+38
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+25
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+42
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+22
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+16
generated by cgit v1.1 at 2024-10-11 01:17:11 +0000