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2018-04-05Fix snafu in aarch64 opcodes debugging statement.binutils-2_28-branchTamar Christina1-1/+7
2017-07-25Bump version.Tristan Gingold1-0/+4
2017-07-25Version 2.28.1Tristan Gingold1-0/+4
2017-07-05[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan1-0/+6
2017-05-05RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark1-0/+5
2017-05-05RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt1-0/+5
2017-03-30RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng1-0/+6
2017-03-30RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng1-0/+4
2017-03-30RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman1-0/+7
2017-03-27PR21303, objdump doesn't show e200z4 insnsAlan Modra1-0/+6
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-0/+8
2017-03-09Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner1-0/+5
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner1-0/+6
2017-03-07Don't decode powerpc insns with invalid fieldsAlan Modra1-0/+12
2017-03-02Set version to 2.28, not a relase.Tristan Gingold1-0/+4
2017-03-02Add generated filesbinutils-2_28Tristan Gingold1-0/+4
2017-02-27Add SFENCE.VMA instructionAndrew Waterman1-0/+5
2017-02-27 sveRichard Sandiford1-0/+48
2017-02-27 sveRichard Sandiford1-0/+9
2017-02-27 sveRichard Sandiford1-0/+5
2017-02-27[AArch64] Add separate feature flag for weaker release consistent load insnsRichard Sandiford1-0/+5
2017-02-11Fix use after free in cgen instruction lookupAlan Modra1-0/+7
2017-02-11POWER9 add scv/rfscv instruction supportNicholas Piggin1-0/+4
2017-01-13Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+13
2017-01-02Update year range in copyright notice of all files.Alan Modra1-0/+4
2017-01-02ChangeLog rotationAlan Modra1-2144/+2
2016-12-28Check bfd support for bfd_mips_elf_get_abiflags in mips make ruleAlan Modra1-0/+11
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-0/+6
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki1-0/+7
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-0/+6
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+15
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki1-0/+5
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki1-0/+5
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki1-0/+12
2016-12-23Bumping version to 2.27.90Tristan Gingold1-0/+4
2016-12-23Regenerate pot files.Tristan Gingold1-0/+4
2016-12-22ChangeLog formatting fixesAlan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman1-0/+4
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki1-0/+7
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+11
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki1-0/+6
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki1-0/+6
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman1-0/+5
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman1-0/+5
2016-12-20Add canonical JALR for RISC-VAndrew Waterman1-0/+5
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman1-0/+5
2016-12-20Formatting changes for RISC-VAndrew Waterman1-0/+4
2016-12-20Add opcodes RISC-V dependenciesAlan Modra1-0/+6
2016-12-19MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki1-0/+5
2016-12-19MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki1-0/+5
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