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2018-04-05Fix snafu in aarch64 opcodes debugging statement.binutils-2_28-branchTamar Christina2-3/+9
2017-07-26S/390: Support z14 as CPU name.Andreas Krebbel1-1/+2
2017-07-25Bump version.Tristan Gingold2-10/+14
2017-07-25Version 2.28.1Tristan Gingold2-10/+14
2017-07-05[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan2-0/+10
2017-05-05RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark2-1/+6
2017-05-05RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt2-1/+6
2017-03-30RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng2-3/+9
2017-03-30RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng2-1/+5
2017-03-30RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman2-4/+11
2017-03-27PR21303, objdump doesn't show e200z4 insnsAlan Modra2-2/+19
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel3-146/+150
2017-03-09Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner2-2/+7
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner2-0/+9
2017-03-07Don't decode powerpc insns with invalid fieldsAlan Modra2-49/+170
2017-03-02Set version to 2.28, not a relase.Tristan Gingold2-10/+14
2017-03-02Add generated filesbinutils-2_28Tristan Gingold18-10/+14
2017-02-27Add SFENCE.VMA instructionAndrew Waterman2-0/+8
2017-02-27 sveRichard Sandiford11-2089/+2815
2017-02-27 sveRichard Sandiford2-6/+17
2017-02-27 sveRichard Sandiford2-0/+21
2017-02-27[AArch64] Add separate feature flag for weaker release consistent load insnsRichard Sandiford2-3/+13
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel3-79/+311
2017-02-11Fix use after free in cgen instruction lookupAlan Modra2-15/+20
2017-02-11POWER9 add scv/rfscv instruction supportNicholas Piggin2-1/+7
2017-01-13Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist8-5344/+5432
2017-01-02Update year range in copyright notice of all files.Alan Modra273-276/+280
2017-01-02ChangeLog rotationAlan Modra2-2144/+2158
2016-12-28Check bfd support for bfd_mips_elf_get_abiflags in mips make ruleAlan Modra7-132/+38
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-0/+15
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki3-20/+25
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-15/+22
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki3-68/+86
2016-12-23MIPS16: Remove "extended" BREAK/SDBBP handlingMaciej W. Rozycki2-2/+6
2016-12-23MIPS16/GAS: Disallow EXTEND delay-slot schedulingMaciej W. Rozycki2-1/+6
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki8-12/+150
2016-12-23Bumping version to 2.27.90Tristan Gingold2-10/+14
2016-12-23Regenerate pot files.Tristan Gingold2-372/+640
2016-12-22ChangeLog formatting fixesAlan Modra1-1/+1
2016-12-22Avoid creating symbol table entries for registersAndrew Waterman2-2/+6
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki2-1/+11
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki3-81/+90
2016-12-20MIPS16/opcodes: Correct 64-bit macros' ISA membershipMaciej W. Rozycki2-6/+12
2016-12-20MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membershipMaciej W. Rozycki2-1/+7
2016-12-20Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman2-22/+27
2016-12-20Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman2-22/+27
2016-12-20Add canonical JALR for RISC-VAndrew Waterman2-0/+8
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+11
2016-12-20Formatting changes for RISC-VAndrew Waterman2-8/+10
2016-12-20Add opcodes RISC-V dependenciesAlan Modra4-0/+14
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