diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/riscv-dis.c | 28 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 33 |
3 files changed, 34 insertions, 32 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e54f440..6a449ff 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2021-01-15 Nelson Chu <nelson.chu@sifive.com> + + * riscv-dis.c: Comments tidy and improvement. + * riscv-opc.c: Likewise. + 2021-01-13 Alan Modra <amodra@gmail.com> * Makefile.in: Regenerate. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c3d9bb8..d6d66e4 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -44,8 +44,8 @@ struct riscv_private_data static const char * const *riscv_gpr_names; static const char * const *riscv_fpr_names; -/* Other options. */ -static int no_aliases; /* If set disassemble as most general inst. */ +/* If set, disassemble as most general instruction. */ +static int no_aliases; static void set_default_riscv_dis_options (void) @@ -179,20 +179,20 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) case 'C': /* RVC */ switch (*++d) { - case 's': /* RS1 x8-x15 */ - case 'w': /* RS1 x8-x15 */ + case 's': /* RS1 x8-x15. */ + case 'w': /* RS1 x8-x15. */ print (info->stream, "%s", riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); break; - case 't': /* RS2 x8-x15 */ - case 'x': /* RS2 x8-x15 */ + case 't': /* RS2 x8-x15. */ + case 'x': /* RS2 x8-x15. */ print (info->stream, "%s", riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); break; - case 'U': /* RS1, constrained to equal RD */ + case 'U': /* RS1, constrained to equal RD. */ print (info->stream, "%s", riscv_gpr_names[rd]); break; - case 'c': /* RS1, constrained to equal sp */ + case 'c': /* RS1, constrained to equal sp. */ print (info->stream, "%s", riscv_gpr_names[X_SP]); break; case 'V': /* RS2 */ @@ -248,11 +248,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) case '<': print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f); break; - case 'T': /* floating-point RS2 */ + case 'T': /* Floating-point RS2. */ print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]); break; - case 'D': /* floating-point RS2 x8-x15 */ + case 'D': /* Floating-point RS2 x8-x15. */ print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); break; @@ -268,7 +268,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) break; case '0': - /* Only print constant 0 if it is the last argument */ + /* Only print constant 0 if it is the last argument. */ if (!d[1]) print (info->stream, "0"); break; @@ -371,7 +371,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) case 'E': { - static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR. */ + static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */ static bfd_boolean init_csr = FALSE; unsigned int csr = EXTRACT_OPERAND (CSR, l); @@ -381,7 +381,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) for (i = 0; i < 4096; i++) riscv_csr_hash[i] = NULL; - /* Set to the newest privilege version. */ + /* Set to the newest privileged version. */ if (default_priv_spec == PRIV_SPEC_CLASS_NONE) default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1; @@ -593,8 +593,6 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) disassembler_ftype riscv_get_disassembler (bfd *abfd) { - /* If -Mpriv-spec= isn't set, then try to set it by checking the elf - privileged attributes. */ if (abfd) { const char *sec_name = get_elf_backend_data (abfd)->obj_attrs_section; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 7c262dd..34aa3c8 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -198,9 +198,9 @@ match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn) const struct riscv_opcode riscv_opcodes[] = { -/* name, xlen, isa, operands, match, mask, match_func, pinfo. */ +/* name, xlen, isa, operands, match, mask, match_func, pinfo. */ {"unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, INSN_ALIAS }, -{"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ +{"unimp", 0, INSN_CLASS_I, "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ {"ebreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, {"ebreak", 0, INSN_CLASS_I, "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, {"sbreak", 0, INSN_CLASS_C, "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, @@ -233,7 +233,7 @@ const struct riscv_opcode riscv_opcodes[] = {"lui", 0, INSN_CLASS_I, "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, {"li", 0, INSN_CLASS_C, "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, {"li", 0, INSN_CLASS_C, "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, -{"li", 0, INSN_CLASS_I, "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ +{"li", 0, INSN_CLASS_I, "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ {"li", 0, INSN_CLASS_I, "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, {"mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, @@ -280,15 +280,13 @@ const struct riscv_opcode riscv_opcodes[] = {"add", 0, INSN_CLASS_C, "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, {"add", 0, INSN_CLASS_C, "d,Cz,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, {"add", 0, INSN_CLASS_I, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, -/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc - applied to an add instruction, for relaxation to use. */ {"add", 0, INSN_CLASS_I, "d,s,t,1",MATCH_ADD, MASK_ADD, match_opcode, 0 }, {"add", 0, INSN_CLASS_I, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, {"la", 0, INSN_CLASS_I, "d,B", 0, (int) M_LA, match_never, INSN_MACRO }, {"lla", 0, INSN_CLASS_I, "d,B", 0, (int) M_LLA, match_never, INSN_MACRO }, {"la.tls.gd", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, {"la.tls.ie", 0, INSN_CLASS_I, "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, -{"neg", 0, INSN_CLASS_I, "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{"neg", 0, INSN_CLASS_I, "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ {"slli", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, {"slli", 0, INSN_CLASS_I, "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, {"sll", 0, INSN_CLASS_C, "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS }, @@ -382,7 +380,7 @@ const struct riscv_opcode riscv_opcodes[] = {"addw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, {"addw", 64, INSN_CLASS_I, "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, {"addw", 64, INSN_CLASS_I, "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, -{"negw", 64, INSN_CLASS_I, "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{"negw", 64, INSN_CLASS_I, "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ {"slliw", 64, INSN_CLASS_I, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 }, {"sllw", 64, INSN_CLASS_I, "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 }, {"sllw", 64, INSN_CLASS_I, "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS }, @@ -395,7 +393,7 @@ const struct riscv_opcode riscv_opcodes[] = {"subw", 64, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, -/* Atomic memory operation instruction subset */ +/* Atomic memory operation instruction subset. */ {"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, {"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, {"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, @@ -485,7 +483,7 @@ const struct riscv_opcode riscv_opcodes[] = {"amomin.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, {"amominu.d.aqrl", 64, INSN_CLASS_A , "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, -/* Multiply/Divide instruction subset */ +/* Multiply/Divide instruction subset. */ {"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, {"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, {"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, @@ -500,7 +498,7 @@ const struct riscv_opcode riscv_opcodes[] = {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, {"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, -/* Bitmanip instruction subset - ZBA/ZBB/ZBC */ +/* Bitmanip instruction subset - ZBA/ZBB/ZBC. */ {"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 }, {"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 }, {"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 }, @@ -548,7 +546,7 @@ const struct riscv_opcode riscv_opcodes[] = {"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 }, {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 }, -/* Single-precision floating-point instruction subset */ +/* Single-precision floating-point instruction subset. */ {"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, {"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, {"fscsr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS }, @@ -629,7 +627,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.s.lu", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, {"fcvt.s.lu", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, -/* Double-precision floating-point instruction subset */ +/* Double-precision floating-point instruction subset. */ {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, @@ -690,7 +688,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, {"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, -/* Quad-precision floating-point instruction subset */ +/* Quad-precision floating-point instruction subset. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, @@ -799,7 +797,7 @@ const struct riscv_opcode riscv_opcodes[] = {"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, -/* Supervisor instructions */ +/* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, INSN_ALIAS }, {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, INSN_ALIAS }, {"csrsi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, INSN_ALIAS }, @@ -838,7 +836,7 @@ const struct riscv_opcode riscv_opcodes[] = /* Instruction format for .insn directive. */ const struct riscv_opcode riscv_insn_types[] = { -/* name, xlen, isa, operands, match, mask, match_func, pinfo. */ +/* name, xlen, isa, operands, match, mask, match_func, pinfo. */ {"r", 0, INSN_CLASS_I, "O4,F3,F7,d,s,t", 0, 0, match_opcode, 0 }, {"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,t", 0, 0, match_opcode, 0 }, {"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,t", 0, 0, match_opcode, 0 }, @@ -932,6 +930,7 @@ const struct riscv_opcode riscv_insn_types[] = {"cb", 0, INSN_CLASS_F_AND_C, "O2,CF3,CS,Cp", 0, 0, match_opcode, 0 }, {"cj", 0, INSN_CLASS_C, "O2,CF3,Ca", 0, 0, match_opcode, 0 }, + /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} }; @@ -939,7 +938,7 @@ const struct riscv_opcode riscv_insn_types[] = /* All standard extensions defined in all supported ISA spec. */ const struct riscv_ext_version riscv_ext_version_table[] = { -/* name, ISA spec, major version, minor_version. */ +/* name, ISA spec, major version, minor version. */ {"e", ISA_SPEC_CLASS_20191213, 1, 9}, {"e", ISA_SPEC_CLASS_20190608, 1, 9}, {"e", ISA_SPEC_CLASS_2P2, 1, 9}, @@ -1001,7 +1000,7 @@ static const struct isa_spec_t isa_specs[] = {"20190608", ISA_SPEC_CLASS_20190608}, {"20191213", ISA_SPEC_CLASS_20191213}, -/* Terminate the list. */ + /* Terminate the list. */ {NULL, 0} }; |