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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/riscv-dis.c2
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e5aa59d..73091b9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-20 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
+ changed.
+
2020-02-19 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 47f9db0..d7a184c 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -326,7 +326,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
unsigned int csr = EXTRACT_OPERAND (CSR, l);
switch (csr)
{
-#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
+#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}