diff options
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/aarch64-asm-2.c | 254 | ||||
-rw-r--r-- | opcodes/aarch64-asm.c | 12 | ||||
-rw-r--r-- | opcodes/aarch64-dis-2.c | 830 | ||||
-rw-r--r-- | opcodes/aarch64-dis.c | 15 | ||||
-rw-r--r-- | opcodes/aarch64-opc-2.c | 2 | ||||
-rw-r--r-- | opcodes/aarch64-opc.c | 16 | ||||
-rw-r--r-- | opcodes/aarch64-opc.h | 2 | ||||
-rw-r--r-- | opcodes/aarch64-tbl.h | 112 |
8 files changed, 877 insertions, 366 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 8bd9816..94e8218 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -651,10 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 122: case 123: case 124: - case 182: + case 125: case 183: case 184: case 185: @@ -668,30 +667,31 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 195: - case 210: + case 196: case 211: case 212: case 213: - case 222: + case 214: case 223: case 224: case 225: case 226: - case 237: - case 241: - case 246: - case 254: - case 255: - case 262: - case 263: + case 227: + case 239: + case 243: + case 248: + case 256: + case 257: case 264: case 265: + case 266: + case 267: return aarch64_ins_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 297: - case 300: + case 120: + case 299: + case 302: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -705,18 +705,17 @@ aarch64_insert_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 302: - return aarch64_ins_reglane (self, info, code, inst, errors); case 39: + case 304: + return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: - case 227: + case 42: case 228: - case 231: - case 266: - case 267: - case 282: - case 283: + case 229: + case 232: + case 268: + case 269: case 284: case 285: case 286: @@ -728,22 +727,23 @@ aarch64_insert_operand (const aarch64_operand *self, case 292: case 293: case 294: + case 295: + case 296: return aarch64_ins_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ins_reglist (self, info, code, inst, errors); case 43: - return aarch64_ins_ldst_reglist (self, info, code, inst, errors); + return aarch64_ins_reglist (self, info, code, inst, errors); case 44: - return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ins_lut_reglist (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ins_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -760,15 +760,15 @@ aarch64_insert_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 88: + case 77: case 89: case 90: case 91: - case 117: - case 121: - case 179: - case 181: - case 202: + case 92: + case 118: + case 122: + case 180: + case 182: case 203: case 204: case 205: @@ -776,103 +776,103 @@ aarch64_insert_operand (const aarch64_operand *self, case 207: case 208: case 209: - case 268: - case 295: - case 296: + case 210: + case 270: + case 297: case 298: - case 299: + case 300: case 301: - case 306: - case 307: + case 303: + case 308: + case 309: return aarch64_ins_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: + case 56: return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); - case 59: - case 169: + case 60: + case 170: return aarch64_ins_fpimm (self, info, code, inst, errors); - case 77: - case 177: - return aarch64_ins_limm (self, info, code, inst, errors); case 78: - return aarch64_ins_aimm (self, info, code, inst, errors); + case 178: + return aarch64_ins_limm (self, info, code, inst, errors); case 79: - return aarch64_ins_imm_half (self, info, code, inst, errors); + return aarch64_ins_aimm (self, info, code, inst, errors); case 80: + return aarch64_ins_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ins_fbits (self, info, code, inst, errors); - case 82: case 83: - case 174: - return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 84: - case 173: case 175: - return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 85: + case 174: + case 176: + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ins_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ins_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ins_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ins_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ins_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ins_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ins_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ins_simd_addr_post (self, info, code, inst, errors); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ins_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ins_pstatefield (self, info, code, inst, errors); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ins_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ins_barrier (self, info, code, inst, errors); + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ins_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ins_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ins_hint (self, info, code, inst, errors); - case 125: case 126: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 127: + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 128: case 129: case 130: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 131: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 132: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 133: + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 134: case 135: case 136: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 137: + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 138: case 139: case 140: @@ -887,8 +887,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 149: case 150: case 151: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 152: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: case 154: case 155: @@ -896,118 +896,120 @@ aarch64_insert_operand (const aarch64_operand *self, case 157: case 158: case 159: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 160: + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: case 162: case 163: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 164: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 166: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 167: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 168: + return aarch64_ins_sve_aimm (self, info, code, inst, errors); + case 169: return aarch64_ins_sve_asimm (self, info, code, inst, errors); - case 170: - return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 171: - return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 172: + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + case 173: return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 180: + case 181: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 196: case 197: case 198: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 199: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 200: case 201: - case 281: + case 202: + case 283: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 214: case 215: case 216: case 217: - return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 218: + return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 219: case 220: case 221: + case 222: return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); - case 229: case 230: - case 232: + case 231: case 233: case 234: case 235: case 236: - return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 237: case 238: + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 240: return aarch64_ins_sve_index_imm (self, info, code, inst, errors); - case 239: + case 241: return aarch64_ins_sve_index (self, info, code, inst, errors); - case 240: case 242: - case 261: - case 308: - case 309: + case 244: + case 263: case 310: + case 311: + case 312: return aarch64_ins_sve_reglist (self, info, code, inst, errors); - case 243: - case 244: - case 247: - case 248: + case 245: + case 246: case 249: case 250: case 251: - case 260: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); - case 245: case 252: case 253: + case 262: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); + case 247: + case 254: + case 255: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 256: case 258: - case 269: + case 260: + case 271: return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); - case 257: case 259: + case 261: return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 270: - case 271: case 272: case 273: case 274: case 275: case 276: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 278: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 279: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 280: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 281: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 282: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 303: - case 304: case 305: + case 306: + case 307: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 311: - case 312: case 313: case 314: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 315: + case 316: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 317: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 57fb861..e738bb4 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -153,10 +153,15 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, { case AARCH64_OPND_QLF_S_4B: case AARCH64_OPND_QLF_S_2H: - /* L:H */ + /* H:L */ assert (reglane_index < 4); insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H); break; + case AARCH64_OPND_QLF_S_2B: + /* H:L:M */ + assert (reglane_index < 8); + insert_fields (code, reglane_index, 0, 3, FLD_M, FLD_L, FLD_H); + break; default: return false; } @@ -180,6 +185,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + assert (reglane_index < 16); + insert_fields (code, reglane_index, 0, 2, FLD_imm3_19, FLD_H); + break; case AARCH64_OPND_QLF_S_H: /* H:L:M */ assert (reglane_index < 8); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index fd19b2d..d327422 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -17285,11 +17285,33 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0001xxxxx010xxxxxxxxxxxxx - fdot. */ - return 2473; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x0xxxxxxxxxx + fdot. */ + return 2473; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0100x1xxxxxxxxxx + fdot. */ + return 3416; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0001xxxxx0101xxxxxxxxxxxx + fmlalb. */ + return 3418; + } } else { @@ -17304,21 +17326,32 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx010xx0xxxxxxxxxx - fmlalb. */ - return 2146; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x0xxxxxxxxxx + fmlalb. */ + return 2146; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx0100x1xxxxxxxxxx + fmlalt. */ + return 2148; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx010xx1xxxxxxxxxx + 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 2148; + return 3428; } } else @@ -17337,11 +17370,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 31) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0011xxxxx010xxxxxxxxxxxxx - bfdot. */ - return 3066; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx0xxxxxxxxxx + bfdot. */ + return 3066; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0011xxxxx010xx1xxxxxxxxxx + fdot. */ + return 3414; + } } else { @@ -17391,31 +17435,108 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0001xxxxx1x0xxxxxxxxxxxxx - fdot. */ - return 2474; + if (((word >> 12) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100000xxxxxxxxxx + fdot. */ + return 2474; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx100010xxxxxxxxxx + fmlallbb. */ + return 3419; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1000x1xxxxxxxxxx + fdot. */ + return 3415; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1100xxxxxxxxxxxx + fmlallbb. */ + return 3420; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0001xxxxx1x01xxxxxxxxxxxx + fmlallbt. */ + return 3421; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx0xxxxxxxxxx - fmlalb. */ - return 2147; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100000xxxxxxxxxx + fmlalb. */ + return 2147; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx100010xxxxxxxxxx + fmlalb. */ + return 3417; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1000x1xxxxxxxxxx + fmlalt. */ + return 2149; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx1100xxxxxxxxxxxx + fmlalltb. */ + return 3424; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0101xxxxx1x0xx1xxxxxxxxxx + 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 2149; + return 3427; } } else @@ -17432,31 +17553,64 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x0011xxxxx1x0xxxxxxxxxxxxx - bfdot. */ - return 3065; + if (((word >> 14) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx0xxxxxxxxxx + bfdot. */ + return 3065; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx100xx1xxxxxxxxxx + fdot. */ + return 3413; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x0011xxxxx110xxxxxxxxxxxxx + fmlallbt. */ + return 3422; + } } else { if (((word >> 31) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx0xxxxxxxxxx - bfmlalb. */ - return 3071; + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx0xxxxxxxxxx + bfmlalb. */ + return 3071; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0111xxxxx100xx1xxxxxxxxxx + bfmlalt. */ + return 3070; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0111xxxxx1x0xx1xxxxxxxxxx - bfmlalt. */ - return 3070; + 011001x0111xxxxx110xxxxxxxxxxxxx + fmlalltt. */ + return 3426; } } else @@ -17762,32 +17916,54 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - if (((word >> 31) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx0xxxxxxxxxx - fmlslb. */ - return 2151; + x11001x0001xxxxx1010xxxxxxxxxxxx + fmlalltb. */ + return 3423; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0x01xxxxx101xx1xxxxxxxxxx - fmlslt. */ - return 2153; + x11001x0001xxxxx1011xxxxxxxxxxxx + fmlalltt. */ + return 3425; } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 111001x0x01xxxxx101xxxxxxxxxxxxx - st1h. */ - return 1954; + if (((word >> 31) & 0x1) == 0) + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx0xxxxxxxxxx + fmlslb. */ + return 2151; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 011001x0101xxxxx101xx1xxxxxxxxxx + fmlslt. */ + return 2153; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 111001x0101xxxxx101xxxxxxxxxxxxx + st1h. */ + return 1954; + } } } else @@ -25976,31 +26152,75 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 13) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx0001xxxxxxxxxx - dup. */ - return 149; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx00001xxxxxxxxxx + dup. */ + return 149; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx00001xxxxxxxxxx + fmaxnm. */ + return 292; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx00001xxxxxxxxxx + fminnm. */ + return 308; + } + } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110010xxxxxxx0001xxxxxxxxxx - fmaxnm. */ - return 292; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x00xxxxxx10001xxxxxxxxxx + fmlallbb. */ + return 3405; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x00xxxxxx10001xxxxxxxxxx + fmlalltb. */ + return 3407; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx0001xxxxxxxxxx - fminnm. */ - return 308; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110x10xxxxxx10001xxxxxxxxxx + fmlallbt. */ + return 3406; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110x10xxxxxx10001xxxxxxxxxx + fmlalltt. */ + return 3408; + } } } } @@ -26209,31 +26429,75 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110x00xxxxxxx1111xxxxxxxxxx - umov. */ - return 152; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxx01111xxxxxxxxxx + umov. */ + return 152; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx01111xxxxxxxxxx + frecps. */ + return 304; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxx01111xxxxxxxxxx + frsqrts. */ + return 316; + } + } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 0x001110010xxxxxxx1111xxxxxxxxxx - frecps. */ - return 304; + 0x001110x00xxxxxx11111xxxxxxxxxx + fdot. */ + return 3397; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110110xxxxxxx1111xxxxxxxxxx - frsqrts. */ - return 316; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxx11111xxxxxxxxxx + fdot. */ + return 3399; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 00001110110xxxxxx11111xxxxxxxxxx + fmlalb. */ + return 3401; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01001110110xxxxxx11111xxxxxxxxxx + fmlalt. */ + return 3402; + } + } } } } @@ -31672,21 +31936,65 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 29) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3013; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111100xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3398; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3013; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111110xxxxxx0000x0xxxxxxxxxx + fmlal. */ + return 3017; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1001111xxxxxxxx0000x0xxxxxxxxxx - fmlal. */ - return 3017; + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx00111101xxxxxx0000x0xxxxxxxxxx + fdot. */ + return 3400; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x000111111xxxxxx0000x0xxxxxxxxxx + fmlalb. */ + return 3403; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x100111111xxxxxx0000x0xxxxxxxxxx + fmlalt. */ + return 3404; + } + } } } else @@ -32216,21 +32524,65 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 30) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3015; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111100xxxxxx1000x0xxxxxxxxxx + fmlallbb. */ + return 3409; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111100xxxxxx1000x0xxxxxxxxxx + fmlalltb. */ + return 3411; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x010111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3015; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x110111110xxxxxx1000x0xxxxxxxxxx + fmlal2. */ + return 3019; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1101111xxxxxxxx1000x0xxxxxxxxxx - fmlal2. */ - return 3019; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0101111x1xxxxxx1000x0xxxxxxxxxx + fmlallbt. */ + return 3410; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1101111x1xxxxxx1000x0xxxxxxxxxx + fmlalltt. */ + return 3412; + } } } } @@ -33681,10 +34033,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 122: case 123: case 124: - case 182: + case 125: case 183: case 184: case 185: @@ -33698,30 +34049,31 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 195: - case 210: + case 196: case 211: case 212: case 213: - case 222: + case 214: case 223: case 224: case 225: case 226: - case 237: - case 241: - case 246: - case 254: - case 255: - case 262: - case 263: + case 227: + case 239: + case 243: + case 248: + case 256: + case 257: case 264: case 265: + case 266: + case 267: return aarch64_ext_regno (self, info, code, inst, errors); case 6: - case 118: case 119: - case 297: - case 300: + case 120: + case 299: + case 302: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -33740,18 +34092,17 @@ aarch64_extract_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 302: - return aarch64_ext_reglane (self, info, code, inst, errors); case 39: + case 304: + return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: - case 227: + case 42: case 228: - case 231: - case 266: - case 267: - case 282: - case 283: + case 229: + case 232: + case 268: + case 269: case 284: case 285: case 286: @@ -33763,22 +34114,23 @@ aarch64_extract_operand (const aarch64_operand *self, case 292: case 293: case 294: + case 295: + case 296: return aarch64_ext_simple_index (self, info, code, inst, errors); - case 42: - return aarch64_ext_reglist (self, info, code, inst, errors); case 43: - return aarch64_ext_ldst_reglist (self, info, code, inst, errors); + return aarch64_ext_reglist (self, info, code, inst, errors); case 44: - return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 45: - return aarch64_ext_lut_reglist (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 46: - return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ext_lut_reglist (self, info, code, inst, errors); case 47: + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); case 48: case 49: case 50: - case 60: + case 51: case 61: case 62: case 63: @@ -33795,16 +34147,16 @@ aarch64_extract_operand (const aarch64_operand *self, case 74: case 75: case 76: - case 87: + case 77: case 88: case 89: case 90: case 91: - case 117: - case 121: - case 179: - case 181: - case 202: + case 92: + case 118: + case 122: + case 180: + case 182: case 203: case 204: case 205: @@ -33812,105 +34164,105 @@ aarch64_extract_operand (const aarch64_operand *self, case 207: case 208: case 209: - case 268: - case 295: - case 296: + case 210: + case 270: + case 297: case 298: - case 299: + case 300: case 301: - case 306: - case 307: + case 303: + case 308: + case 309: return aarch64_ext_imm (self, info, code, inst, errors); - case 51: case 52: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 53: + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 54: case 55: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 56: + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); + case 57: return aarch64_ext_shll_imm (self, info, code, inst, errors); - case 59: - case 169: + case 60: + case 170: return aarch64_ext_fpimm (self, info, code, inst, errors); - case 77: - case 177: - return aarch64_ext_limm (self, info, code, inst, errors); case 78: - return aarch64_ext_aimm (self, info, code, inst, errors); + case 178: + return aarch64_ext_limm (self, info, code, inst, errors); case 79: - return aarch64_ext_imm_half (self, info, code, inst, errors); + return aarch64_ext_aimm (self, info, code, inst, errors); case 80: + return aarch64_ext_imm_half (self, info, code, inst, errors); + case 81: return aarch64_ext_fbits (self, info, code, inst, errors); - case 82: case 83: - case 174: - return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 84: - case 173: case 175: - return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 85: + case 174: + case 176: + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 86: + case 87: return aarch64_ext_cond (self, info, code, inst, errors); - case 92: - case 101: - return aarch64_ext_addr_simple (self, info, code, inst, errors); case 93: - return aarch64_ext_addr_regoff (self, info, code, inst, errors); + case 102: + return aarch64_ext_addr_simple (self, info, code, inst, errors); case 94: + return aarch64_ext_addr_regoff (self, info, code, inst, errors); case 95: case 96: - case 98: - case 100: - return aarch64_ext_addr_simm (self, info, code, inst, errors); case 97: - return aarch64_ext_addr_simm10 (self, info, code, inst, errors); case 99: + case 101: + return aarch64_ext_addr_simm (self, info, code, inst, errors); + case 98: + return aarch64_ext_addr_simm10 (self, info, code, inst, errors); + case 100: return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); - case 102: - return aarch64_ext_addr_offset (self, info, code, inst, errors); case 103: - return aarch64_ext_simd_addr_post (self, info, code, inst, errors); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 104: + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 105: - return aarch64_ext_sysreg (self, info, code, inst, errors); case 106: - return aarch64_ext_pstatefield (self, info, code, inst, errors); + return aarch64_ext_sysreg (self, info, code, inst, errors); case 107: + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 108: case 109: case 110: case 111: case 112: - return aarch64_ext_sysins_op (self, info, code, inst, errors); case 113: - case 115: - return aarch64_ext_barrier (self, info, code, inst, errors); + return aarch64_ext_sysins_op (self, info, code, inst, errors); case 114: - return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); case 116: + return aarch64_ext_barrier (self, info, code, inst, errors); + case 115: + return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); + case 117: return aarch64_ext_prfop (self, info, code, inst, errors); - case 120: + case 121: return aarch64_ext_hint (self, info, code, inst, errors); - case 125: case 126: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 127: + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 128: case 129: case 130: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 131: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 132: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 133: + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 134: case 135: case 136: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 137: + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 138: case 139: case 140: @@ -33925,8 +34277,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 149: case 150: case 151: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 152: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 153: case 154: case 155: @@ -33934,119 +34286,121 @@ aarch64_extract_operand (const aarch64_operand *self, case 157: case 158: case 159: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 160: + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 161: case 162: case 163: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 164: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 165: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 166: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 167: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 168: + return aarch64_ext_sve_aimm (self, info, code, inst, errors); + case 169: return aarch64_ext_sve_asimm (self, info, code, inst, errors); - case 170: - return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 171: - return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 172: + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + case 173: return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); - case 176: + case 177: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 178: + case 179: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 180: + case 181: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 196: case 197: case 198: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 199: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 200: case 201: - case 281: + case 202: + case 283: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 214: case 215: case 216: case 217: - return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 218: + return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 219: case 220: case 221: + case 222: return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); - case 229: case 230: - case 232: + case 231: case 233: case 234: case 235: case 236: - return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 237: case 238: + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 240: return aarch64_ext_sve_index_imm (self, info, code, inst, errors); - case 239: + case 241: return aarch64_ext_sve_index (self, info, code, inst, errors); - case 240: case 242: - case 261: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); - case 243: case 244: - case 247: - case 248: + case 263: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); + case 245: + case 246: case 249: case 250: case 251: - case 260: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); - case 245: case 252: case 253: + case 262: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); + case 247: + case 254: + case 255: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 256: case 258: - case 269: + case 260: + case 271: return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); - case 257: case 259: + case 261: return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 270: - case 271: case 272: case 273: case 274: case 275: case 276: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 277: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 278: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 279: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 280: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 281: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 282: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 303: - case 304: case 305: + case 306: + case 307: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); - case 308: - case 309: case 310: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 311: case 312: + return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 313: case 314: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 315: + case 316: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 317: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 045af49..6098204 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -402,6 +402,12 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); info->reglane.regno &= 0x1f; break; + case AARCH64_OPND_QLF_S_2B: + /* h:l:m */ + info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, + FLD_M); + info->reglane.regno &= 0xf; + break; default: return false; } @@ -422,7 +428,15 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, return 0; switch (info->qualifier) { + case AARCH64_OPND_QLF_S_B: + /* H:imm3 */ + info->reglane.index = extract_fields (code, 0, 2, FLD_H, + FLD_imm3_19); + info->reglane.regno &= 0x7; + break; + case AARCH64_OPND_QLF_S_H: + case AARCH64_OPND_QLF_S_2B: if (info->type == AARCH64_OPND_Em16) { /* h:l:m */ @@ -437,6 +451,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, } break; case AARCH64_OPND_QLF_S_S: + case AARCH64_OPND_QLF_S_4B: /* h:l */ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); break; diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 71f6824..5e1bd1c 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -63,6 +63,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V7"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm1_14}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm2_13}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm3_12}, "a SIMD vector without a type qualifier encoding a bit index"}, @@ -258,6 +259,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index b704673..b42b809 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -310,6 +310,7 @@ const aarch64_field fields[] = { 22, 2 }, /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ { 12, 1 }, /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */ + { 10, 2 }, /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -367,6 +368,7 @@ const aarch64_field fields[] = { 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */ { 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */ { 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */ + { 19, 3 }, /* imm3_19: general immediate in bits [21:19]. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ @@ -818,6 +820,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] = {4, 1, 0x2, "s", OQK_OPD_VARIANT}, {8, 1, 0x3, "d", OQK_OPD_VARIANT}, {16, 1, 0x4, "q", OQK_OPD_VARIANT}, + {2, 1, 0x0, "2b", OQK_OPD_VARIANT}, {4, 1, 0x0, "4b", OQK_OPD_VARIANT}, {4, 1, 0x0, "2h", OQK_OPD_VARIANT}, @@ -1816,6 +1819,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: size = get_operand_fields_width (get_operand_from_code (type)); @@ -3234,12 +3238,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, 01 0:Rm 10 M:Rm 11 RESERVED */ - if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H + if (type == AARCH64_OPND_Em16 + && (qualifier == AARCH64_OPND_QLF_S_H + || qualifier == AARCH64_OPND_QLF_S_2B) && !value_in_range_p (opnd->reglane.regno, 0, 15)) { set_regno_out_of_range_error (mismatch_detail, idx, 0, 15); return 0; } + if (type == AARCH64_OPND_Em8 + && !value_in_range_p (opnd->reglane.regno, 0, 7)) + { + set_regno_out_of_range_error (mismatch_detail, idx, 0, 7); + return 0; + } break; case AARCH64_OPND_CLASS_MODIFIED_REG: @@ -4127,6 +4139,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_En: case AARCH64_OPND_Em: case AARCH64_OPND_Em16: + case AARCH64_OPND_Em8: case AARCH64_OPND_SM3_IMM2: snprintf (buf, size, "%s[%s]", style_reg (styler, "v%d.%s", opnd->reglane.regno, @@ -4254,6 +4267,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm3_19_INDEX: case AARCH64_OPND_SVE_Zm3_12_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm3_10_INDEX: case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 8804e7c..ba6b407 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -114,6 +114,7 @@ enum aarch64_field_kind FLD_SVE_i3h3, FLD_SVE_i3l, FLD_SVE_i3l2, + FLD_SVE_i4l2, FLD_SVE_imm3, FLD_SVE_imm4, FLD_SVE_imm5, @@ -171,6 +172,7 @@ enum aarch64_field_kind FLD_imm3_12, FLD_imm3_14, FLD_imm3_15, + FLD_imm3_19, FLD_imm4_0, FLD_imm4_5, FLD_imm4_10, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5876592..da17fa3 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2218,6 +2218,10 @@ { \ QLF3(S_S,S_B,S_B), \ } +#define OP_SVE_VVV_H_B \ +{ \ + QLF3(S_H,S_B,S_B), \ +} #define OP_SVE_VVV_Q_D \ { \ QLF3(S_Q,S_D,S_D), \ @@ -2467,6 +2471,20 @@ QLF3(V_4S, V_16B, S_4B),\ } +/* e.g. FDOT <Vd>.4H, <Vn>.8B, <Vm>.8B. */ +#define QL_V3DOTH \ +{ \ + QLF3(V_4H, V_8B, V_8B), \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FDOT <Vd>.4H, <Vn>.8B, <Vm>.2B[<index>]. */ +#define QL_V2DOTH \ +{ \ + QLF3(V_4H, V_8B, S_2B),\ + QLF3(V_8H, V_16B, S_2B),\ +} + /* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D. */ #define QL_SHA512UPT \ { \ @@ -2533,6 +2551,30 @@ QLF3(V_4S, V_4H, S_H),\ } +/* e.g. FMLALB <Vd>.8H, <Vn>.16B, <Vm>.16B. */ +#define QL_V3FML8H \ +{ \ + QLF3(V_8H, V_16B, V_16B),\ +} + +/* e.g. FMLALB <Vd>.8H, <Vn>.16B, <Vm>.B. */ +#define QL_V2FML8H \ +{ \ + QLF3(V_8H, V_16B, S_B),\ +} + +/* e.g. FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.16B. */ +#define QL_V3FMLL4S \ +{ \ + QLF3(V_4S, V_16B, V_16B),\ +} + +/* e.g. FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.B. */ +#define QL_V2FMLL4S \ +{ \ + QLF3(V_4S, V_16B, S_B),\ +} + /* e.g. RMIF <Xn>, #<shift>, #<mask>. */ #define QL_RMIF \ { \ @@ -2768,6 +2810,18 @@ static const aarch64_feature_set aarch64_feature_brbe = AARCH64_FEATURE (BRBE); static const aarch64_feature_set aarch64_feature_sme_lutv2 = AARCH64_FEATURES (3, SME_LUTv2, SME2, SME2p1); +static const aarch64_feature_set aarch64_feature_fp8fma = + AARCH64_FEATURE (FP8FMA); +static const aarch64_feature_set aarch64_feature_fp8dot4 = + AARCH64_FEATURE (FP8DOT4); +static const aarch64_feature_set aarch64_feature_fp8dot2 = + AARCH64_FEATURE (FP8DOT2); +static const aarch64_feature_set aarch64_feature_fp8fma_sve = + AARCH64_FEATURES (2, FP8FMA_SVE, SVE); +static const aarch64_feature_set aarch64_feature_fp8dot4_sve = + AARCH64_FEATURES (2, FP8DOT4_SVE, SVE); +static const aarch64_feature_set aarch64_feature_fp8dot2_sve = + AARCH64_FEATURES (2, FP8DOT2_SVE, SVE); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2846,6 +2900,12 @@ static const aarch64_feature_set aarch64_feature_sme_lutv2 = #define LUT_SVE2 &aarch64_feature_lut_sve2 #define BRBE &aarch64_feature_brbe #define LUTv2_SME2 &aarch64_feature_sme_lutv2 +#define FP8FMA &aarch64_feature_fp8fma +#define FP8DOT4 &aarch64_feature_fp8dot4 +#define FP8DOT2 &aarch64_feature_fp8dot2 +#define FP8FMA_SVE &aarch64_feature_fp8fma_sve +#define FP8DOT4_SVE &aarch64_feature_fp8dot4_sve +#define FP8DOT2_SVE &aarch64_feature_fp8dot2_sve #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -3049,6 +3109,18 @@ static const aarch64_feature_set aarch64_feature_sme_lutv2 = #define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \ FLAGS, 0, 0, NULL } +#define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8DOT2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2, OPS, QUALS, FLAGS, 0, 0, NULL } +#define FP8FMA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8FMA_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT4_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -6639,6 +6711,41 @@ const struct aarch64_opcode aarch64_opcode_table[] = LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0), LUTv2_SME2_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Zdnx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0), LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX2_12, SVE_Zt), {}, 0), + /* FP8 multiplication AdvSIMD instructions. */ + FP8DOT4_INSN("fdot", 0x0e00fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + FP8DOT4_INSN("fdot", 0x0f000000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0e40fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOTH, F_SIZEQ), + FP8DOT2_INSN("fdot", 0x0f400000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em16), QL_V2DOTH, F_SIZEQ), + FP8FMA_INSN("fmlalb", 0x0ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4ec0fc00, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0), + FP8FMA_INSN("fmlalb", 0x0fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlalt", 0x4fc00000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FML8H, 0), + FP8FMA_INSN("fmlallbb", 0x0e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x0e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x4e00c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x4e40c400, 0xffe0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0), + FP8FMA_INSN("fmlallbb", 0x2f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlallbt", 0x2f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltb", 0x6f008000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + FP8FMA_INSN("fmlalltt", 0x6f408000, 0xffc0f400, asimdsame, OP3 (Vd, Vn, Em8), QL_V2FMLL4S, 0), + + /* FP8 multiplication SVE instructions. */ + FP8DOT4_SVE_INSNC("fdot", 0x64608400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT4_SVE_INSNC("fdot", 0x64604400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64208400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8DOT2_SVE_INSNC("fdot", 0x64204400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64a08800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalb", 0x64205000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x64208800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbb", 0x6420c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x64209800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlallbt", 0x6460c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x6420a800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltb", 0x64a0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x6420b800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalltt", 0x64e0c000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), + FP8FMA_SVE_INSNC("fmlalt", 0x64a05000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0), {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -6715,6 +6822,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a SIMD vector element") \ Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ "a SIMD vector element limited to V0-V15") \ + Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD_Rm), \ + "a SIMD vector element limited to V0-V7") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, F(FLD_Rm, FLD_imm1_14), \ "a SIMD vector without a type qualifier encoding a bit index") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, F(FLD_Rm, FLD_imm2_13), \ @@ -7138,6 +7247,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_quad_index, "SVE_Zm3_10_INDEX", \ + 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3), \ + "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ "an indexed SVE vector register") \ |